Non-Uniform Stress Layer Fabrication for MOSFET Yield
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for fabricating stress layers in MOSFETs face limitations in increasing tensile stress without causing the stress layer to fracture, which reduces the yield of MOSFETs, as the maximum tensile stress value is 1.52 GPa and exceeding this leads to layer fracture.
Innovation Solution
A method involving a low temperature deposition process to form a first tensile stress layer on a semiconductor substrate, followed by a high temperature annealing process to densify it, and then forming a second tensile stress layer with stress concentrated on a transition portion of the first layer, which has a non-uniform thickness, allowing for effective stress transfer to the channel region without exceeding the maximum stress value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the tensile stress of the stress layer is increased to further raise the operation speed, then the carrier mobility is improved, but the stress layer is likely to fracture and the yield is reduced
Solution Approach 1:
The stress layer is designed with non-uniform thickness, where the first region (over the channel) has greater thickness and provides higher tensile stress to enhance carrier mobility, while the second region (at the edge) has reduced thickness to avoid fracture. This local variation in thickness allows different regions to serve different functions: the channel region receives maximum stress for speed improvement, while the edge region maintains structural integrity for yield improvement.
2Strength
If the tensile stress of the stress layer is increased beyond 1.52 GPa, then the carrier mobility can be further enhanced, but the stress layer will fracture
Solution Approach 1:
The stress layer exhibits spatially varying thickness to achieve local optimization of stress magnitude versus structural stability. The thicker first region delivers the required high tensile stress (up to 1.52 GPa or slightly above in controlled conditions) for enhanced carrier mobility, while the thinner second region maintains integrity and prevents catastrophic failure, thus preserving overall layer stability.
Solution Approach 2:
The stress layer is effectively segmented into two functional regions based on thickness: a first region with greater thickness for high stress application and a second region with reduced thickness for structural support. This segmentation allows the system to simultaneously achieve high local stress where needed while maintaining global structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility by concentrating tensile stress on the transition portion, effectively increasing the interstitial space in the channel region without causing the stress layer to fracture, thereby improving MOSFET performance without exceeding the maximum tensile stress limit.
Implementation Method 1
a low temperature deposition process to form a first tensile stress layer on a transistor within the first transistor region
Implementation Method 2
a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process
Implementation Method 3
the inherent stress within the stress region can be therefore transferred or applied to a channel region right below the gate structure. This tensile stress can enlarge the interstitial space within the lattice structure and raise the carrier mobility
Data Source
AI summary
A method of fabrication a transistor device with a non-uniform stress layer including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.). Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a tensile stress lower than a tensile stress of the second tensile stress layer.