MOSFET Stress Layer Structure for Thin-Gate Mobility Gain
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Solution Overview
Problem
The miniaturization of MOSFETs leads to thinner gate electrodes, resulting in reduced stress application from stress application layers, which in turn decreases carrier mobility due to planarization of these layers, and this issue is not effectively addressed in fin-type MOSFETs with double or triple-gate electrodes.
Innovation Solution
A semiconductor device with a field effect transistor structure where a first stress application layer is applied over the gate electrode, and a second stress application layer is formed over the source/drain region, applying different stresses to improve carrier mobility by adjusting the combination of stresses applied to the channel forming region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If gate electrode materials are made thinner to improve miniaturization, then device integration density is improved, but stress application to the channel forming region is reduced
Solution Approach 1:
The stress application layer is extended from a single planar layer into a three-dimensional structure that wraps around the gate electrode. This includes forming the stress application layer on the top surface and extending it down the sidewalls, effectively adding a vertical dimension to stress application. This dimensional transition allows the stress application layer to maintain effective stress contact with the channel region even when the gate electrode thickness is reduced, thereby resolving the contradiction between miniaturization and stress application effectiveness.
Solution Approach 2:
The stress application layer is positioned to surround and enclose portions of the gate electrode structure, creating a nested configuration where the stress layer contains the gate electrode. This nesting arrangement ensures that the stress application layer remains in close proximity to the channel forming region regardless of gate thickness variations, maintaining effective stress transfer while allowing the gate electrode to be scaled down for miniaturization.
2Manufacturing precision
If stress application layer is planarized to improve manufacturing, then manufacturing precision is improved, but stress localization to channel forming region is reduced
Solution Approach 1:
The stress application layer is configured with spatially varying thickness and orientation to provide different stress characteristics in different locations. The layer is thicker and wraps around the gate electrode sidewalls in regions where stress localization is critical, while being thinner in other areas. This local quality variation enables simultaneous achievement of manufacturing feasibility and effective stress localization to the channel forming region, resolving the contradiction between planarization and stress localization.
3Area of moving object
If gate electrode becomes thinner, then device miniaturization is improved, but driving performance is reduced due to reduced stress effect
Solution Approach 1:
By transitioning the stress application layer from a planar configuration to a three-dimensional wrapped structure that extends along the gate electrode sidewalls, the invention maintains effective stress application to the channel region even as gate electrode thickness is reduced for miniaturization. This dimensional change ensures that carrier mobility enhancement is preserved, thereby maintaining driving performance despite device scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility by effectively applying stresses to the channel forming region, improving the driving performance of transistors compared to traditional methods, even as gate electrodes become thinner.
Implementation Method 1
a technique of increasing carrier mobility by applying stress to a channel forming region of a transistor using a stress application layer
Data Source
AI summary
A semiconductor device includes a field effect transistor including: a semiconductor substrate including a channel forming region; a gate insulating film formed at the channel forming region on the semiconductor substrate; a gate electrode formed over the gate insulating film; a first stress application layer formed over the gate electrode and applying stress to the channel forming region; a source/drain region formed on a surface layer portion of the semiconductor substrate at both sides of the gate electrode and the first stress application layer; and a second stress application layer formed over the source/drain region in a region other than at least a region of the first stress application layer and applying stress different from the first stress application layer to the channel forming region.