MOSFET Cell Layout With Striated Channels for Lower ON-Resistance
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Solution Overview
Problem
Conventional power MOSFETs face high ON-state resistance due to limitations in fabricating optimal source contact and channel region geometries, leading to increased conduction losses and reduced efficiency.
Innovation Solution
The design incorporates a cellular structure with increased channel region area relative to the n+/p-well and source contact regions, oriented to minimize resistance by maximizing channel area and spacing between cells, thereby reducing ON-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional MOSFET cell geometries are used with standard n+/p-well and source contact regions, then fabrication is simplified, but ON-state resistance increases due to insufficient channel region area
Solution Approach 1:
The device is divided into multiple identical cell structures arranged in an array, where each cell contains segmented n+/p-well regions, source contact regions, and channel regions. This segmentation allows optimization of the channel region area in each cell while maintaining overall device performance through the combined effect of multiple cells
Solution Approach 2:
The patent applies local quality by creating specific geometric configurations within each cell - the n+/p-well regions are positioned to define channel regions with optimized dimensions and shapes. The channel regions are given specific local characteristics (area, aspect ratio) that differ from conventional designs to minimize resistance, while other regions like the drift region maintain uniform properties across the device
2Loss of energy
If the channel region area is increased relative to n+/p-well and source contact regions, then ON-state resistance decreases, but cell geometry becomes more complex and harder to fabricate
Solution Approach 1:
The patent employs asymmetric geometry within each cell - the n+/p-well regions are positioned asymmetrically to create elongated channel regions with optimized aspect ratios. This asymmetric arrangement maximizes the channel area available for current flow while maintaining a manageable number of fabrication steps, avoiding the need for completely symmetric or overly complex patterns
3Loss of energy
If pitch between cells is reduced to increase channel region density, then ON-state resistance decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes cell geometry by utilizing two-dimensional space efficiently within each cell - creating elongated channel regions that extend in specific directions and positioning n+/p-well regions to maximize channel area without requiring reduction in pitch. This dimensional optimization allows achieving low resistance with standard pitch dimensions, avoiding the need for ultra-precise pitch control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in lower ON-state resistance and improved efficiency by increasing channel density and optimizing channel orientation, reducing conduction losses compared to conventional designs.
Implementation Method 1
Appropriate biasing creates an electrical field that attracts charge carriers into the channel which then provides a conductive path between the source and drain
Implementation Method 2
drain to source current conduction through the wafer, which eliminates current and reduces the on-state resistance
Data Source
AI summary
A semiconductor device cell includes a semiconductor layer having a surface defining a series of parallel striations extending in a first direction. The semiconductor layer surface has a lower electrical resistance in the first direction than in a second direction orthogonal to the first direction. A channel region defines a set of first channel region segments extending in the first direction, and a set of second channel region segments extending in the second direction. The first channel region segments and the second channel region segments are arranged to maximize portions of the channel region extending in the first direction across the surface, and minimize portions of the channel region extending in the second direction, to reduce or minimize the effective electrical resistance of the channel region in operation.