Vertical Power MOSFET Substrate Grooves for Low Rdson
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Solution Overview
Problem
The high drain-source on resistance (Rdson) of power MOSFETs contributes significantly to power consumption, with the silicon substrate being a major contributor, and existing methods have not effectively reduced this resistance.
Innovation Solution
The method involves using an etching barrier layer between the substrate and epitaxial layer, employing electric-chemical etching, and forming bottom grooves in the substrate to reduce the substrate's contribution to Rdson, while also using dopants and metal layers for improved electrical contact and reduced defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the silicon substrate is removed or reduced, then the Rdson is reduced, but the mechanical support and structural integrity are compromised
Solution Approach 1:
The patent extracts the silicon substrate contribution to Rdson by forming bottom grooves that remove substrate material beneath the active regions. This extraction reduces the substrate's resistive contribution while the remaining substrate between grooves maintains structural integrity. The etching barrier layer enables selective removal of substrate in specific regions without compromising overall device strength.
Solution Approach 2:
The substrate is segmented into active regions with bottom grooves and inactive regions with etching barrier layers. This segmentation allows different treatments in different areas: substrate removal in active regions reduces Rdson, while substrate retention in inactive regions maintains mechanical support. The segmentation resolves the contradiction by spatially separating the functions of low resistance and structural strength.
2Loss of energy
If electric-chemical etching is used to remove substrate, then the Rdson is reduced, but the process complexity increases
Solution Approach 1:
The etching barrier layer acts as an intermediary that enables selective substrate removal. It mediates between the etching process and the substrate, allowing etching to proceed in active regions while protecting inactive regions. This intermediary simplifies the overall process by providing a clear stop criterion for etching, preventing the need for complex multi-step removal processes.
Solution Approach 2:
The patent changes the electrical parameters during etching by applying reverse bias to the PN junction at the etching barrier layer interface. This parameter change (applying voltage) controls the etching rate and stop point, enabling precise substrate removal. The electrical parameter control simplifies the etching process compared to purely chemical or mechanical methods, as it provides a self-limiting etch that stops automatically at the junction.
3Loss of energy
If bottom grooves are formed in the substrate, then the substrate contribution to Rdson is reduced, but the manufacturing steps increase
Solution Approach 1:
The etching barrier layer is formed preliminarily before substrate etching, establishing the stop criterion in advance. This preliminary action (forming the barrier layer during epitaxial growth or as a separate step) enables subsequent selective substrate removal without requiring complex real-time monitoring or multiple etching steps. The preliminary barrier layer formation simplifies the overall manufacturing sequence.
Solution Approach 2:
The etching process is self-limiting due to the PN junction at the etching barrier layer interface. When reverse bias is applied, the etching automatically stops at the junction without requiring precise timing control or external intervention. This self-service characteristic of the etching process improves manufacturing efficiency by eliminating the need for complex process control systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the Rdson of power MOSFETs by minimizing the substrate's impact, leading to lower power consumption and improved electrical properties.
Implementation Method 1
The main principle of the electric-chemical etching method is to use a PN junction generated at the interface of an N-type semiconductor slab and a P-type semiconductor slab to implement electric-chemical etching on a semiconductor slab that needs to be etched under a reverse biased condition
Data Source
AI summary
The invention relates to a power semiconductor device and its preparation methods thereof. Particularly, the invention aims at providing a method for reducing substrate contribution to the Rdson (drain-source on resistance) of power MOSFETs, and a power MOSFET device made by the method. By forming one or more bottom grooves at the bottom of Si substrate, the on resistance of the power MOSFET device attributed to the substrate is effectively reduced. A matching lead frame base complementary to the substrate with bottom grooves further improves the package of the power MOSFET device.