Power MOSFET Super Junction with Trench Gate
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Solution Overview
Problem
Power MOSFETs with vertical electrode structures face a tradeoff between breakdown voltage and on-resistance, limiting their performance in low power consumption applications, and the trench gate structure results in poor gate controllability due to reduced gate-to-drain capacitance.
Innovation Solution
A semiconductor device with a super junction structure is developed, featuring alternately arranged n-type and p-type pillar layers and a trench gate configuration, where an n-type layer with higher impurity concentration is introduced between the pillar layers to enhance breakdown voltage and reduce on-resistance, while maintaining improved gate controllability by managing capacitance ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If the impurity dope concentration of the drift layer is increased to reduce on-resistance, then the on-resistance decreases, but the breakdown voltage decreases due to the p-n junction breakdown limit
Solution Approach 1:
The drift layer is segmented into multiple regions with different impurity concentrations: a first drift layer region with lower impurity concentration (maintaining high breakdown voltage) and a second drift layer region with higher impurity concentration (reducing on-resistance). This spatial segmentation allows each region to fulfill different functional requirements simultaneously.
Solution Approach 2:
Different regions of the drift layer are assigned different local properties: the first drift layer region has low impurity concentration optimized for breakdown voltage, while the second drift layer region has high impurity concentration optimized for low on-resistance. This local quality differentiation resolves the global tradeoff by optimizing each region for its specific function.
2Productivity
If a trench gate structure is adopted to enable miniaturization, then the device can be scaled down, but the gate-to-drain capacitance decreases at lower voltage causing poor gate controllability and switching noise
Solution Approach 1:
The drift layer is differentiated into regions with different impurity concentrations to locally optimize electrical characteristics. The second drift layer region with higher impurity concentration specifically addresses the gate controllability issue by modifying the capacitance characteristics in the trench gate region, allowing miniaturization while maintaining operational control.
Solution Approach 2:
The impurity concentration parameter is changed in the second drift layer region to alter the electrical characteristics, specifically the capacitance behavior. This parameter change ensures that the gate-to-drain capacitance maintains appropriate levels for good controllability even in the miniaturized trench gate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves a superior tradeoff between breakdown voltage and on-resistance, reducing switching noise and improving controllability, thereby enhancing the performance and reliability of power MOSFETs.
Implementation Method 1
a structure is known in which a p-type pillar layer and an n-type pillar layer are embedded in the drift layer what is called a 'super junction structure'. In this super junction structure, by making the amount of charge (impurity amount) included in the p-type pillar layer and the n-type pillar layer the same, a pseudo-non-doped layer is created, and a current is passed through the highly doped n-type pillar layer while holding a high breakdown voltage.
Implementation Method 2
the more reducing a periodic cycle in the lateral direction, the more the impurity concentration of the n-type pillar layer can be increased
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type, a control electrode, a first main electrode, a second main electrode, and a sixth semiconductor layer of the first conductivity type. The second semiconductor layer and the third semiconductor layer are alternately provided on the first semiconductor layer in a direction substantially parallel to a major surface of the first semiconductor layer. The fourth semiconductor layer is provided on the second semiconductor layer and the third semiconductor layer. The fifth semiconductor layer is selectively provided on a surface of the fourth semiconductor layer. The control electrode is provided in a trench via an insulating film. The trench penetrates through the fourth semiconductor layer from a surface of the fifth semiconductor layer and is in contact with the second semiconductor layer. The first main electrode is connected to the first semiconductor layer. The second main electrode is connected to the fourth semiconductor layer and the fifth semiconductor layer. The sixth semiconductor layer is provided between the fourth semiconductor layer and the second semiconductor layer. An impurity concentration of the sixth semiconductor layer is higher than an impurity concentration of the second semiconductor layer.