MOSFET Solid-State Switch Circuit for Leakage Compensation

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Solution Overview

Problem

Solid state switches, particularly MOSFETs, suffer from parasitic capacitance and current leakage that negatively impact measurement performance and efficiency in precision instruments.

Innovation Solution

A MOS-based switch design incorporating additional circuitry, including buffers connected to the bulk terminals of MOS devices in series, to compensate for current leakage by maintaining a voltage equal to the drain voltage at the bulk terminal, thereby reducing or eliminating leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a solid state switch is used in precision measurement apparatus, then the switch can control current flow effectively, but current leakage occurs at the input and output terminals which reduces measurement accuracy

Engineering Contradiction:
Improveswitch control functionVSAvoidmeasurement accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

A buffer circuit is introduced as an intermediary component between the input terminal and the bulk terminal of the FET. This buffer acts as a mediator that senses the voltage at the input terminal and replicates it at the bulk terminal, thereby eliminating the voltage difference that causes leakage current. The buffer circuit includes operational amplifiers and resistors configured to provide voltage feedback to the bulk terminal, effectively reducing leakage without compromising the switch's control function.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Power

If a solid state switch is used to control current flow, then switching functionality is achieved, but leakage current reduces power efficiency

Engineering Contradiction:
Improveswitching capabilityVSAvoidpower efficiency
Core Design Contradiction:
PowerVSLoss of energy

Solution Approach 1:

The buffer circuit implements a feedback mechanism where the voltage at the input terminal is continuously monitored and fed back to the bulk terminal through the operational amplifier. This feedback loop dynamically adjusts the bulk terminal voltage to match the input voltage, ensuring that the voltage difference across the channel is minimized. As a result, leakage current is reduced, improving power efficiency while maintaining full switching capability.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If additional circuitry is added to compensate for leakage, then leakage current is reduced, but device complexity increases

Engineering Contradiction:
Improveleakage compensationVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Instead of adding complex active compensation circuits or multiple transistors, the invention uses a buffer circuit as a simple intermediary that leverages the existing FET structure. The buffer consists of standard operational amplifiers and resistors that are commonly available in precision measurement equipment, making the added complexity manageable while achieving effective leakage compensation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed design significantly reduces current leakage at the input and output terminals, improving power efficiency and measurement accuracy in precision instruments.

Implementation Method 1

a first buffer comprising an output terminal coupled to the bulk terminal of the first FET, and an input terminal coupled to the first terminal of the first FET

Methodology Applied
Scientific EffectVoltage buffering:

Data Source

PatentEP4607796A1Solid state switch and a circuit
Publication Date: 2025.08.27 ANALOG DEVICES INT UNLTD CO
  • EP4607796A1 patent drawingFigure 1a~1b
  • EP4607796A1 patent drawingFigure 2
  • EP4607796A1 patent drawingFigure 3~4a

AI summary

A solid state switch, comprising a first field-effect transistor (FET). The first FET has a first terminal, a second terminal, a bulk terminal and a gate terminal, and is configured to be switched between an on-state and an off-state. The solid state switch also comprises a second FET in series with the first FET. The second FET has a first terminal, a second terminal, a bulk terminal, and a gate terminal. The second terminal of the first FET is connected to the second terminal of the second FET. The solid state switch comprises a first buffer comprises an output terminal coupled to the bulk terminal of the first FET, and an input terminal coupled to the first terminal of the first FET.