High-Isolation MOSFET Switch Layout With Lower Parasitic Capacitance
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Solution Overview
Problem
Existing high isolation switch circuits in integrated circuits require multiple switches in series, leading to increased parasitic capacitance, limited operating frequency range, and higher power consumption.
Innovation Solution
A two-to-one input switch network utilizing n-type metal-oxide-semiconductor field-effect transistors (MOSFETs) with specific layout techniques to achieve high isolation, reducing the need for additional isolation devices and minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple switches in series are used to achieve high isolation, then isolation performance is improved, but parasitic capacitance increases and operating frequency range is limited
Solution Approach 1:
The patent combines multiple switch functions into a single switch device with integrated isolation capability. The single switch incorporates internal structures that provide both switching function and isolation performance, eliminating the need for separate series switches and reducing total parasitic capacitance while maintaining high isolation performance.
Solution Approach 2:
The patent introduces a vertical dimension to the switch structure by implementing stacked transistor configurations and three-dimensional layout techniques. This allows isolation functions to be achieved through vertical stacking rather than horizontal series connection, reducing the overall footprint and parasitic capacitance while maintaining isolation performance.
2Reliability
If multiple switches in series are used to achieve high isolation, then isolation performance is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple switch functions into a single integrated switch device, reducing the total number of active devices from multiple switches to one. This consolidation reduces the cumulative power consumption of control signals, gate drivers, and leakage currents while maintaining the required isolation performance through integrated design structures.
3Reliability
If the size of series pass switches is increased to provide comparable resistance, then isolation is improved, but parasitic capacitance increases four times
Solution Approach 1:
The patent transitions from horizontal series connection to vertical stacking architecture. By arranging transistor channels vertically in stacked configurations, the design achieves comparable resistance with smaller individual device sizes, reducing total parasitic capacitance while maintaining isolation performance through the vertical dimension.
Solution Approach 2:
The patent changes the geometric parameters of the switch devices by using scaled-down transistor dimensions in vertical stacks. This allows achieving the required resistance values with smaller device areas, thereby reducing parasitic capacitance while maintaining isolation through the stacked configuration rather than increasing individual device sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution achieves high isolation with reduced power consumption and increased operating frequency range by minimizing the number of active devices and parasitic capacitance in the switch circuit.
Implementation Method 1
a channel formed between a source and a drain of the transistor when a gate voltage is applied to the gate
Implementation Method 2
good isolation can be achieved by using two switches in series with a ground shunt switch placed between them... the total parasitic capacitance of these two series switches in combination with the shunt switch is about four times larger
Data Source
Figure 1A~1B
Figure 2A
Figure 2B
AI summary
An embodiment integrated circuit includes a switch and a conductive line over the switch. The switch includes a gate, a first source/drain region at a top surface of a semiconductor substrate, and a second source/drain region at the top surface of the semiconductor substrate. The first source/drain region and the second source/drain region are disposed on opposing sides of the gate. At least a portion of the first conductive line is aligned with the gate, and the first conductive line is electrically coupled to ground.