MOSFET Switch Well Tracking for Low Insertion Loss
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Solution Overview
Problem
MOSFET switches face issues with over/under voltage effects leading to catastrophic failures, particularly during power down operations, and existing designs struggle with high insertion loss and limited bandwidth due to the body effect and capacitance-related frequency roll-off.
Innovation Solution
The solution involves forming an internal power rail for primary FETs, coupling their wells to the higher local power supply or input signal, and using additional FETs in series to cancel capacitance effects, ensuring the drain/source to well diode junctions are not forward biased during power down, thereby reducing insertion loss and enhancing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the well is connected to a fixed power supply voltage, then the MOSFET switch provides low on-resistance during normal operation, but the drain/source to well diode becomes forward biased during power down, causing harmful current paths and leakage
Solution Approach 1:
The well connection is changed from static (fixed to power supply) to dynamic (tracks the higher of power supply or input signal). This dynamic adjustment prevents the drain/source to well diode from becoming forward biased during power down operations, eliminating harmful current paths while maintaining low on-resistance during normal operation.
Solution Approach 2:
The well voltage parameter is changed from a fixed value to a variable that adapts to operating conditions. By making the well voltage track the higher of the power supply or input signal, the patent adjusts the electrical parameters to prevent diode forward biasing during power down while maintaining optimal switching performance during operation.
2Ease of manufacture
If the well capacitance is present in the MOSFET structure, then the device provides simple construction, but the capacitance causes frequency roll-off, reducing bandwidth
Solution Approach 1:
An intermediary circuit is introduced between the well and the input signal. This intermediary actively manages the well voltage to counteract the capacitive coupling effects, preventing the well capacitance from causing frequency roll-off while maintaining the simplicity of the basic MOSFET structure.
3Reliability
If additional circuitry is added to prevent forward biasing during power down, then protection against harmful effects is improved, but device complexity increases
Solution Approach 1:
The well tracking circuit serves multiple functions simultaneously: it prevents diode forward biasing during power down, maintains optimal threshold voltage during operation, and protects against over/under voltage effects. This multi-functionality achieves reliable protection without significantly increasing device complexity.
Data Source
AI summary
An FET switch comprising a single or parallel opposite polarity FETS is illustrated with wells that are driven from internal power rails. The internal power rails are logically coupled by other driving FET switches to, in one case, the higher of a positive power supply or signal level wherein the well of the PMOS FET switch will not allow the drain/source to well diode to be forward biased. In a second case, a second power rail is logically coupled to the lower of either and input signal or ground, wherein the well of the NMOS FET will not allow the drain/source to well diode to be forward biased.