MOSFET Top Doped Region Gradient for Breakdown Voltage
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Solution Overview
Problem
Ultra high voltage semiconductor devices face a challenge in maintaining high breakdown voltage while minimizing on-state resistance due to current accumulation at interdigitated source and drain terminals, which increases layout area and decreases breakdown voltage.
Innovation Solution
A metal oxide semiconductor field transistor design featuring a top doped region with a dopant concentration gradient between the source and drain regions, formed through a single ion implantation process using a patterned mask, which reduces on-state resistance and enhances breakdown voltage by distributing the electric field effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If interdigitated finger structures are used for source and drain regions, then layout area is reduced, but current accumulation occurs at terminals which decreases breakdown voltage
Solution Approach 1:
The patent applies local quality by creating a top doped region with specific dopant concentration gradient only in the critical area between source and drain terminals, rather than uniformly doping the entire device. This localized doping structure modifies the electric field distribution specifically where current accumulation occurs, enhancing breakdown voltage without changing the interdigitated finger layout that reduces area.
2Ease of manufacture
If uniform dopant concentration is used in top doped region, then fabrication is simplified, but electric field distribution is suboptimal reducing breakdown voltage
Solution Approach 1:
The patent implements parameter changes by introducing a dopant concentration gradient in the top doped region, transitioning from uniform concentration to graded concentration. This gradient structure (with higher dopant concentration near the drain and lower near the source) optimizes the electric field distribution, thereby enhancing breakdown voltage while maintaining compatibility with standard ion implantation fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively increases breakdown voltage and reduces on-state resistance by distributing the dopant concentration gradient across multiple regions, preventing current accumulation and improving device performance without increasing fabrication costs or complexity.
Implementation Method 1
An ion implantation process is performed to form a top doped region in the substrate by using the patterned mask layer as a mask
Data Source
AI summary
A metal oxide semiconductor field transistor including a gate electrode, a gate dielectric layer, a source region, a drain region, and a top doped region are provided. The drain region of a first conductivity type is located in a substrate. The source region of the first conductivity type is located in the substrate and surrounded the drain region. The gate electrode is located above the substrate between the source region and the drain region. The gate dielectric layer is located between the gate electrode and the substrate. The top doped region of a second conductivity type is located in the substrate between the gate electrode and the drain region. The top doped region includes at least three regions. Each of the three regions has a dopant concentration gradient and a concentration gradually decreased from a region adjacent the gate electrode to a region adjacent the drain region.