MOSFET Trench Gate Segmentation for Low Parasitic Capacitance

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Solution Overview

Problem

MOSFETs face trade-offs in optimizing device parameters such as on-resistance (RDSON) and breakdown voltage (BVDSS), where improvements in one parameter often degrade others, like increasing parasitic capacitance.

Innovation Solution

The formation of a trench and conductive structure within a semiconductor device, including a vertically-oriented conductive region and a horizontally-oriented doped region, allows for improved charge carrier flow directionality, reducing parasitic capacitance and maintaining low RDSON while enhancing breakdown voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional MOSFET structures are used to improve on-resistance (RDSON), then RDSON decreases, but parasitic capacitance increases and breakdown voltage (BVDSS) decreases

Engineering Contradiction:
Improveon-resistance (RDSON)VSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent segments the drain region into multiple discrete drain contacts separated by isolation trenches, rather than using a single large drain contact. This segmentation reduces the overlap area between the drain and gate, thereby reducing parasitic capacitance while maintaining low on-resistance through multiple parallel current paths

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces vertical isolation trenches that extend into the substrate, adding a vertical dimension to the isolation strategy. This vertical segmentation effectively reduces the lateral overlap between conductive regions, reducing parasitic capacitance without increasing the planar footprint

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7902017B2Process of forming an electronic device including a trench and a conductive structure therein
Publication Date: 2011.03.08 SEMICON COMPONENTS IND LLC
  • US7902017B2 patent drawing
  • US7902017B2 patent drawing
  • US7902017B2 patent drawing

AI summary

A process of forming an electronic device can include providing a workpiece comprising a substrate, including an underlying doped region, and a semiconductor layer overlying the underlying doped region, wherein the semiconductor layer has a primary surface spaced apart from the underlying doped region. The process can also include forming a vertically-oriented conductive region extending from the primary surface to the underlying doped region, and forming a horizontally-oriented doped region adjacent to the primary surface. In a finished form of the electronic device, the horizontally-oriented doped region extends further in a lateral direction toward a region where a source region has been or will be formed, as compared to the vertically-oriented conductive region. The electronic device includes a transistor that includes the underlying doped region, the vertically-oriented conductive region, and the horizontally-oriented doped region.