MOSFET Trench Insulating Layer Reduces On-Resistance and Breakdown Voltage Trade-off
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Solution Overview
Problem
In optimizing MOSFET performance, existing device structures and fabrication processes often face trade-offs where improvements in one parameter, such as on-resistance times area (RDSON*Area), result in degradation of other parameters like breakdown voltage (BVDSS) and increased parasitic capacitance, making it difficult to simultaneously lower RDSON and gate charge.
Innovation Solution
The implementation of a transistor structure with a lateral channel region and vertically-oriented doped regions adjacent to trenches, featuring a thicker insulating layer to reduce capacitive coupling and leverage self-aligned processing, which allows for smaller feature sizes and improved performance by minimizing misalignment errors, including the formation of conductive structures within trenches and the use of a superjunction in an alternative embodiment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional MOSFET structures are used to improve on-resistance times area (RDSON*Area), then breakdown voltage (BVDSS) is reduced and parasitic capacitance increases
Solution Approach 1:
The drain region is segmented into multiple vertically-oriented doped regions separated by trenches containing conductive structures. This segmentation allows each region to be independently optimized, enabling lower on-resistance through multiple parallel conduction paths while maintaining high breakdown voltage through the insulating layers between segments that prevent avalanche breakdown.
Solution Approach 2:
The invention transitions from conventional lateral device structures to a vertical architecture where doped regions extend vertically into the semiconductor layer. This dimensional change enables increased device density and reduced on-resistance without proportionally increasing device area, while the vertical trenches provide electrical isolation that maintains breakdown voltage.
2Quantity of substance
If conventional MOSFET structures are used to improve on-resistance times area (RDSON*Area), then parasitic capacitance increases
Solution Approach 1:
Insulating layers are deposited within the trenches to electrically isolate the conductive structures from each other and from adjacent doped regions. This extraction of electrical coupling between regions reduces parasitic capacitance while the multiple vertical doped regions continue to provide low on-resistance paths.
3Quantity of substance
If feature sizes are reduced to improve performance, then misalignment errors increase
Solution Approach 1:
The trenches and insulating layers are formed before depositing the conductive structures. This preliminary structuring creates self-aligned features where subsequent conductive layers automatically align to the pre-formed trench boundaries, eliminating misalignment errors that would otherwise occur with smaller features and reducing the need for tight lithographic tolerances.
Solution Approach 2:
The insulating layers within trenches serve dual functions: they provide electrical isolation between conductive structures and simultaneously act as alignment references for subsequent processing steps. The self-aligned nature of the trench formation means that the insulating layer automatically defines the precise location and dimensions of isolated regions without requiring additional alignment steps.
Data Source
AI summary
An electronic device can include a semiconductor layer overlying a substrate and having a primary surface and a thickness, wherein a trench extends through at least approximately 50% of the thickness of semiconductor layer to a depth. The electronic device can further include a conductive structure within the trench, wherein the conductive structure extends at least approximately 50% of the depth of the trench. The electronic device can still further include a vertically-oriented doped region within the semiconductor layer adjacent to and electrically insulated from the conductive structure; and an insulating layer disposed between the vertically-oriented doped region and the conductive structure. A process of forming an electronic device can include patterning a semiconductor layer to define a trench extending through at least approximately 50% of the thickness of the semiconductor layer and forming a vertically-oriented doped region after patterning the semiconductor layer to define the trench.