MOSFET Trench Isolation Edge Insulating Layer Leakage Prevention
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Solution Overview
Problem
The existing trench isolation techniques in semiconductor devices, such as STI structures, suffer from a thinning phenomenon of the gate oxide layer due to compressive stress and nitride liner-induced issues, leading to edge crowding, charge trapping, and increased leakage current, which affects the performance of high voltage transistors.
Innovation Solution
A MOS Field Effect Transistor with a trench isolation region is designed to include an edge insulating layer thicker than the gate insulating layer, comprising a triple-layered structure of oxide and nitride layers, which prevents dent formation and electric field concentration at the boundary between the trench isolation and active regions, thereby inhibiting leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a trench isolation structure with nitride liner is used, then device isolation is achieved, but gate oxide layer thinning occurs due to compressive stress
Solution Approach 1:
The patent applies different insulating layer configurations to different regions: a thicker edge insulating layer is formed at the boundary between the trench isolation region and active region, while a standard gate insulating layer is used in the channel region. This local differentiation prevents stress concentration at the boundary while maintaining proper gate control in the active region.
Solution Approach 2:
The edge insulating layer is formed in advance before the gate electrode is deposited. This preliminary action ensures that the thicker insulating layer is already in place to prevent dent formation and stress concentration before subsequent processing steps occur.
2Ease of manufacture
If thermal oxidation is performed to form gate oxide layer, then gate insulating layer is created, but oxide layer thinning occurs at trench boundary due to stress and nitride liner
Solution Approach 1:
The patent implements a local quality approach by forming an edge insulating layer with greater thickness specifically at the trench boundary region, while maintaining standard thickness in the channel region. This localized differentiation addresses the stress concentration issue at the boundary without affecting the gate control characteristics in the active region.
Solution Approach 2:
The edge insulating layer acts as an intermediary structure between the trench isolation region and the active region. It mediates the stress distribution and prevents direct stress transmission to the gate oxide layer at the boundary, thereby preventing thinning and dent formation.
3Reliability
If nitride liner is formed in STI structure, then trench isolation is achieved, but charge trapping occurs and leakage current increases
Solution Approach 1:
The patent applies different insulating layer configurations to different regions: a thicker edge insulating layer is formed at the boundary between the trench isolation region and active region, while a standard gate insulating layer is used in the channel region. This local differentiation prevents stress concentration at the boundary while maintaining proper gate control in the active region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents leakage current and maintains the threshold voltage of transistors by ensuring a robust edge insulating layer structure, enhancing the reliability and performance of semiconductor devices.
Implementation Method 1
a compressive stress induced on a silicon substrate caused by (i) oxidation of the surface of the silicon substrate and a sidewall of the STI structure
Implementation Method 2
oxidation of the surface of the silicon substrate and a sidewall of the STI structure
Data Source
AI summary
A leakage current occurring on a boundary of a trench isolation region and an active region can be prevented in a Metal Oxide Semiconductor (MOS) Field Effect transistor, and a fabricating method thereof is provided. The transistor includes the trench isolation region disposed in a predetermined portion of a semiconductor substrate to define the active region. A source region and a drain region are spaced apart from each other within the active region with a channel region disposed between the source region and the drain region. A gate electrode crosses over the channel region between the source region and the drain region, and a gate insulating layer is disposed between the gate electrode and the channel region. An edge insulating layer thicker than the gate insulating layer is disposed on a lower surface of the gate electrode around the boundary of the trench isolation region and the active region.