Super Junction Vertical MOSFET Gate Trench Self-Alignment
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Solution Overview
Problem
In the manufacturing of vertical power MOSFETs with a super junction structure, misalignment during lithography and excessive lateral diffusion of impurities can lead to increased ON resistance due to narrowing of the n-type semiconductor region, affecting the device's performance.
Innovation Solution
A manufacturing method where an n-type column is formed directly under the gate trench by introducing n-type impurities using a mask that defines the trench, ensuring self-aligned positioning and preventing misalignment with the p-type column, thereby maintaining the desired width of the n-type column as a current path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithography technique and ion implantation method are used to form p-type column, then manufacturing process can be completed, but misalignment occurs between gate trench and p-type column due to lithography alignment errors
Solution Approach 1:
The gate trench structure itself serves as the alignment reference for forming the n-type column. By using the same mask that defines the gate trench to introduce n-type impurities, the system uses its own structure as the reference, eliminating the need for separate alignment processes and ensuring precise self-alignment between the gate trench and n-type column.
Solution Approach 2:
The gate trench is formed first using photolithography and etching, establishing a precise structural reference before the n-type column formation. This preliminary action creates the alignment基准 that guides subsequent impurity introduction, ensuring that the n-type column is positioned accurately relative to the gate trench without requiring additional alignment steps.
2Device complexity
If conventional photolithography alignment is used, then manufacturing process is simplified, but n-type column width is narrowed due to misalignment, increasing ON resistance
Solution Approach 1:
The mask that defines the gate trench automatically defines the n-type column position and width. The gate trench structure serves its dual function as both the gate electrode support and the alignment reference for n-type column formation, eliminating width variation caused by separate alignment processes while maintaining manufacturing simplicity.
3Productivity
If device features are scaled down to improve performance, then device density increases, but alignment errors have greater impact on n-type column width and ON resistance
Solution Approach 1:
The self-aligned approach using the gate trench as reference ensures that the n-type column width is determined by the mask dimensions rather than alignment accuracy. This eliminates the scaling penalty where alignment errors would otherwise have proportionally greater impact on narrower features, allowing consistent width control across different device density levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces ON resistance while securing high breakdown voltage, improving the overall performance of the semiconductor device by ensuring accurate placement and width of the n-type column, even as device features become finer.
Implementation Method 1
a step of forming a gate trench in an upper surface of a semiconductor substrate including an n-type semiconductor layer and a p-type semiconductor layer on the n-type semiconductor layer by an etching method using a mask
Implementation Method 2
a step of forming an n-type column reaching the n-type semiconductor layer by introducing an n-type impurity into a bottom portion of the gate trench using the mask
Data Source
AI summary
An improved structure and a manufacturing method of a vertical type power MOSFET having a super junction configuration is disclosed. The improved structure and the manufacturing method of the vertical type power MOSFET comprising: a step of preparing a semiconductor substrate SB including an n-type semiconductor layer SL and a p-type epitaxial layer EP on the semiconductor layer SL; a step of forming a trench GT in the p-type epitaxial layer EP by using an etching mask with a predetermined opening width; and a step of introducing an n-type impurity into a bottom portion of the trench GT using the etching mask with the predetermined opening width, whereby forming an n-type column NC at the bottom of trench GT and reaching the semiconductor layer SL.