MOSFET Trench Spacer Layout for Sub-Micron Cell Pitch
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Solution Overview
Problem
Current technologies face challenges in producing power semiconductor devices with reduced cell pitch, as they rely heavily on lithography definition and alignment tolerance to avoid source-gate short-circuiting, and misalignment can lead to threshold voltage imbalance and device performance degradation.
Innovation Solution
A method of manufacturing a semiconductor power device involves forming trench regions with a mesa region in between, etching the trenches to create spacers, and forming insulating and conductive regions. This method allows for precise alignment of contacts and regions without additional lithography steps, enabling reduced cell pitch and improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lithography definition and alignment tolerance are used to avoid source-gate short-circuiting, then device reliability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The spacer structure performs self-alignment automatically during the etching process. The spacer width, defined by conformal deposition thickness, directly determines the contact-to-trench distance without requiring additional lithography alignment steps. This self-service mechanism eliminates the need for complex alignment tolerance control while maintaining device reliability.
Solution Approach 2:
The spacer acts as an intermediary element between the trench region and the source contact. It provides a physical reference that mediates the positioning relationship, ensuring accurate spacing without direct reliance on lithography alignment between separate features. This intermediary structure simplifies the manufacturing process by decoupling the alignment requirements.
2Productivity
If cell pitch is reduced to increase device density, then productivity is improved, but manufacturing precision requirements worsen
Solution Approach 1:
The invention transitions the critical dimension control from the lateral lithography plane to the vertical deposition plane. Instead of controlling contact-to-trench distance through lateral lithography alignment, the distance is controlled by the vertical thickness of the spacer layer deposited conformally on the trench sidewalls. This dimensional shift enables reduced cell pitch with relaxed lithography precision requirements.
Solution Approach 2:
The critical parameter for spacing control changes from lateral dimensions (controlled by lithography) to vertical film thickness (controlled by deposition). By changing the controlling parameter from in-plane alignment to out-of-plane thickness, the manufacturing precision requirements are shifted to a process with better controllability, enabling sub-micron cell pitch fabrication.
3Productivity
If contact-to-trench distance is reduced to decrease cell pitch, then device density is improved, but risk of source-gate short-circuiting increases
Solution Approach 1:
The spacer structure is formed preliminarily before the source contact is created. This preliminary spacer defines the minimum safe distance between the trench and contact in advance, preventing source-gate short-circuiting before the contact formation step. The pre-established spacer acts as a built-in protective barrier that eliminates short-circuit risk even at reduced cell pitch.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables the production of semiconductor devices with sub-micron cell pitch, improves manufacturing tolerance, and enhances device ruggedness and on-resistance, while preventing source-gate short-circuiting.
Implementation Method 1
The insulating region and the spacers may have a high etch selectivity. In other words, the materials used for the insulating region and the spacers may etch at significantly different etch rates when exposed to a given etchant.
Implementation Method 2
the mesa region extends above an upper surface of each trench region
Data Source
AI summary
A method of manufacturing a semiconductor power device is provided. The method includes forming at least two trench regions within a semiconductor region, etching each trench region so that the mesa region extends above an upper surface of each trench region, and forming a plurality of spacers, where the spacers are located over each trench region and are adjacent to the mesa region.