MOSFET Vertical Contact Layouts for Parasitic Capacitance Reduction
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Solution Overview
Problem
As MOSFET devices are miniaturized, the parasitic capacitance between closely spaced contacts increases, affecting their operation and requiring improved layouts and structures to reduce this capacitance and enhance performance.
Innovation Solution
The MOSFET devices are designed with specific layouts and structures that include aligned gate, source, and drain contacts extending in particular directions, with optimized spacings and arrangements to minimize parasitic capacitance, such as zigzag patterns and staggered alignments, which increase contact lengths and spacings to reduce capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If MOSFET devices are reduced in size, then device dimensions and area are improved, but parasitic capacitance between contacts increases
Solution Approach 1:
The patent transforms the traditional planar contact layout into a three-dimensional vertical structure. Contacts are arranged in multiple layers (first contacts in a first plane, second contacts in a second plane) separated by an insulating layer, utilizing the vertical dimension to increase spatial separation between contacts that are horizontally adjacent, thereby reducing parasitic capacitance while maintaining compact footprint
Solution Approach 2:
An insulating layer is introduced as an intermediary between the first contacts and second contacts. This intermediate layer physically separates the conductive elements, preventing direct capacitive coupling and reducing parasitic capacitance between adjacent contacts in the multi-plane structure
2Area of stationary object
If contacts are closely spaced to reduce device area, then area is improved, but parasitic capacitance increases
Solution Approach 1:
The patent resolves the area-capacitance tradeoff by moving contact separation from the horizontal plane to the vertical dimension. Contacts are arranged in multiple stacked planes with insulating layers between them, allowing horizontal proximity for area efficiency while achieving vertical separation for capacitance reduction
Solution Approach 2:
Thin insulating films are used to separate contact planes vertically. These thin film layers provide sufficient electrical isolation to reduce parasitic capacitance while occupying minimal space, enabling the compact multi-plane contact structure
Data Source
AI summary
A metal-oxide-semiconductor field-effect transistor device includes a first active area, a first gate electrode configured to cross the first active area and extend in a Y direction, and define a first source area and a first drain area, first gate contacts disposed on the first gate electrode to align on a first virtual gate passing line extending in the Y direction, first source contacts disposed on the first source area to align on a first virtual source passing line extending in the Y direction, and first drain contacts disposed on the first drain area to align on a first virtual drain passing line extending in the Y direction, wherein at least one of the first drain contacts is disposed to align on any one of first virtual X-straight lines configured to pass between the first source contacts and extend parallel in an X direction perpendicular to the Y direction.