Trench Gate MOSFET Well Overlap Reduces Electric Field Concentration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power semiconductor devices with trench gate MOSFETs face a challenge in maintaining high breakdown voltage due to electric field concentration at the edge or corner of the gate electrode, leading to reduced device performance.
Innovation Solution
The design includes a trench gate power MOSFET with a self-aligned source region and gate electrode, where the gate electrode shape decreases in height from the trench side wall, and a well overlapping the trench edge to ensure a uniform carrier distribution, reducing electric field concentration and enhancing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a trench gate MOSFET is used to reduce device area, then the MOSFET occupies a smaller area, but electric field concentration occurs at the gate electrode edge leading to reduced breakdown voltage
Solution Approach 1:
The patent applies local quality by creating a well region with different doping characteristics specifically at the trench corner area. This well region has a different impurity concentration and type compared to the surrounding drift layer, locally modifying the electric field distribution precisely where the concentration problem occurs at the gate electrode edge, thereby resolving the breakdown voltage issue without changing the overall device area.
Solution Approach 2:
The patent introduces a vertical dimension solution by forming a well region that extends from the surface into the drift layer at the trench corner. This three-dimensional structure modifies the electric field distribution in the vertical direction, creating a gradual transition zone that prevents field concentration at the horizontal gate edge, thus maintaining high breakdown voltage while preserving the compact trench gate structure.
2Manufacturing precision
If the gate electrode is self-aligned in the trench, then manufacturing precision is improved, but electric field concentration at the trench edge reduces breakdown voltage
Solution Approach 1:
The well region is specifically positioned at the trench corner area where self-aligned gate electrodes create field concentration. This localized modification with different doping properties addresses the electrical field distribution problem at the critical corner region while preserving the self-aligned manufacturing advantage, as the well formation is integrated into the existing self-aligned process sequence.
Solution Approach 2:
The well region acts as an intermediary structure between the gate electrode and the drift layer at the trench corner. It provides a transition zone with intermediate doping characteristics that mediates the electric field distribution, preventing direct field concentration at the gate edge while maintaining the self-aligned geometric relationship established during manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents or reduces electric field concentration at the trench edges, resulting in a power MOSFET with low on-resistance and high breakdown voltage, suitable for high-power applications.
Implementation Method 1
forming a drift layer doped with a first type impurity on a semiconductor substrate doped with the first type impurity by epitaxially growth
Implementation Method 2
forming a gate insulation layer on the trench
Implementation Method 3
forming a gate insulation layer on the trench
Implementation Method 4
doped with a first type impurity
Implementation Method 5
doped with a first type impurity
Data Source
AI summary
A semiconductor device includes a drift layer including a trench formed on a semiconductor substrate. A well in the drift layer overlaps an edge of the trench, and at least one gate electrode is formed at this overlapping edge region. The drift layer and semiconductor may be doped with a first type of impurity and the well may be doped with a second type of impurity. Through this arrangement, an improved distribution of carriers may be formed in the drift layer.