MOSFET Well-PID Protection Using Floating-Gate Bias Control
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Solution Overview
Problem
Plasma-induced damage (PID) is a significant reliability issue in semiconductor manufacturing, particularly affecting metal-oxide semiconductor field-effect transistors (MOSFETs), as it leads to circuit degradation and variability, and existing solutions fail to effectively address well-PID across all process generations and designs, especially when considering direct current (DC), electrostatic discharge (ESD), and PID situations.
Innovation Solution
The implementation of MOS-based design solutions that include a control circuit connected to the gate of a MOSFET, allowing the gate to float during fabrication to discharge accumulated charge, and subsequently biasing off the MOSFET to prevent current flow, thereby reducing or eliminating well-PID, with options for various well-PID protection circuits suitable for different voltage applications and technology nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If device-level solutions are implemented to address well-PID, then PID protection is improved, but device complexity increases
Solution Approach 1:
The MOSFET's own structure is utilized to protect against well-PID by allowing the gate to float during fabrication, enabling the device to discharge accumulated charge through its intrinsic parasitic diode without requiring external protection circuits
Solution Approach 2:
The control circuit is designed to provide multiple functions: it biases off the MOSFET during normal operation to prevent leakage current, and can be disconnected to allow the gate to float during fabrication for charge discharge, making a single circuit serve both operational and fabrication protection needs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces or eliminates well-PID with minimal impact on area or functionality, no concerns regarding electrostatic discharge, and suitability for all designs and technology nodes, including advanced finFET and planar processes, thereby enhancing the reliability and performance of semiconductor devices.
Implementation Method 1
During manufacturing, the gate of the MOSFET floats such that accumulated charge in the well region discharges through the MOSFET
Implementation Method 2
In operation of the device, the control circuit is connected to the gate of the MOSFET to bias off the MOSFET and prevent current from flowing through the MOSFET
Data Source
AI summary
A circuit includes a substrate, p-well regions over the substrate and including n- channel metal-oxide semiconductor field-effect transistors, n-well regions over the substrate and including p-channel metal-oxide semiconductor field-effect transistors, drain/source regions of protection metal-oxide semiconductor field-effect transistors, and at least one control circuit. First conductive connections connect selected drain/source regions to the p-well regions and the n-well regions, second conductive connections connect selected n-channel metal-oxide semiconductor field-effect transistors and p-channel metal-oxide semiconductor field-effect transistors to one another, and third conductive connections are configured to connect gates of the protection metal-oxide semiconductor field-effect transistors to the at least one control circuit.