P Type MOSFET Work Function Tuning via Dopant Dipoles
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Solution Overview
Problem
The integration of metal gates and high K gate dielectric layers in P type MOSFETs faces challenges such as thermal stability and interfacial states, particularly due to the Fermi-Pinning Effect, making it difficult to achieve an adequately low threshold voltage.
Innovation Solution
A method involving the formation of source/drain regions, an interfacial oxide layer, a high K gate dielectric layer, and a metal gate layer, with dopant implantation and annealing to adjust the effective work function by distributing dopants at the interfaces, generating electrical dipoles and altering the characteristics of the gate stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a high K gate dielectric layer is used to reduce gate leakage current, then gate leakage is reduced, but it becomes difficult to achieve an adequately low threshold voltage due to the Fermi-Pinning Effect
Solution Approach 1:
The patent changes the work function parameter of the metal gate by selecting specific metal materials (such as tungsten, titanium nitride, tantalum nitride) and adjusting their thickness, along with controlling doping concentrations in the semiconductor substrate, to achieve the desired threshold voltage range while maintaining low gate leakage current through the high K dielectric layer
Solution Approach 2:
The patent employs a composite gate structure consisting of a metal gate layer combined with a high K gate dielectric layer (such as HfO2, ZrO2, or their silicates/nitrides), creating a composite material system that simultaneously provides the low leakage properties of the high K dielectric and the adjustable work function of the metal gate, overcoming the limitations of either material alone
2Length of moving object
If the feature size of MOSFETs is continuously decreased to advance semiconductor technology, then device scaling is achieved, but severe gate current leakage occurs
Solution Approach 1:
The patent changes the dielectric constant parameter by adopting high K gate dielectric materials (with K > 3.9, such as HfO2 with K≈25, ZrO2 with K≈25) to replace conventional SiO2, enabling the physical thickness to be increased while maintaining the same equivalent oxide thickness (EOT), thus reducing gate leakage current in scaled devices
Solution Approach 2:
The patent replaces the conventional Poly-Si gate, which suffers from depletion effect and boron penetration issues at scaled dimensions, with a metal gate structure that eliminates these problems, providing a more reliable solution for continued device scaling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the adjustment of the effective work function of P type MOSFETs, enhancing stability and reliability by achieving the desired threshold voltage range of 4.8 eV to 5.2 eV.
Implementation Method 1
dopants accumulated at the lower interface of the high K gate dielectric can generate the electrical dipoles of proper polarity through the interfacial reaction
Implementation Method 2
performing annealing to change an effective work function of a gate stack comprising the first metal gate layer, the high K gate dielectric layer, and the interfacial oxide layer
Data Source
AI summary
Provided are P type MOSFETs and methods for manufacturing the same. The method may include forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopants into the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack including the first metal gate layer, the high K gate dielectric, and the interfacial oxide layer.