MoSi-TiSi Contact Stack for Low-Resistance NMOS and PMOS
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Solution Overview
Problem
As semiconductor devices approach advanced nodes below the 2 nm node, there is a need to reduce contact resistance to improve speed and drive current, particularly in NMOS and PMOS transistors, where existing methods fail to effectively lower contact resistance, especially with molybdenum being a p-type metal that increases contact resistance when used alone in NMOS contacts.
Innovation Solution
Integrating molybdenum silicide (MoSi) with titanium silicide (TiSi) layers on both n and p transistors, followed by a capping layer and optional annealing in a hydrogen atmosphere, to form a semiconductor structure that reduces contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If molybdenum silicide (MoSi) is used alone in NMOS contacts, then the contact resistance increases, but if it is integrated with titanium silicide (TiSi), then the contact resistance is reduced
Solution Approach 1:
The patent applies composite materials by integrating molybdenum silicide (MoSi) and titanium silicide (TiSi) layers to form a multi-layer contact structure. This composite approach combines the properties of both materials: MoSi provides good adhesion to silicon and appropriate work function, while TiSi contributes to reduced contact resistance. The synergistic combination achieves lower contact resistance than either material alone, resolving the technical contradiction between reliability improvement and device complexity increase.
Solution Approach 2:
The patent merges two separate metal silicide layers (MoSi and TiSi) into a unified contact structure. By depositing MoSi first followed by TiSi, and optionally annealing them together, the patent creates an integrated contact system where both materials work together to reduce contact resistance. This merging principle allows the contact structure to benefit from both materials' properties simultaneously, achieving the desired reduction in contact resistance despite the increased structural complexity.
2Area of moving object
If the transistor size is reduced to increase circuit density, then the footprint decreases, but the contact resistance increases
Solution Approach 1:
The patent uses composite materials (MoSi and TiSi layers) to address the contact resistance issue that arises with transistor scaling. As transistors are reduced in size to increase circuit density, the contact resistance tends to increase. The multi-layer silicide structure provides enhanced electrical properties that compensate for the reduced transistor dimensions, maintaining low contact resistance even as the transistor footprint decreases.
Solution Approach 2:
The patent changes the material parameters of the contact structure by introducing a multi-layer silicide system with different work functions and electrical properties. By adjusting the composition, thickness, and thermal treatment of the MoSi and TiSi layers, the patent optimizes the contact resistance parameter to work effectively with scaled-down transistor dimensions, thereby resolving the contradiction between reduced footprint and increased contact resistance.
3Ease of manufacture
If a single metal silicide layer is used, then the manufacturing process is simpler, but the contact resistance reduction is insufficient
Solution Approach 1:
The patent merges two deposition processes into a single integrated manufacturing sequence. By depositing MoSi and TiSi in succession without breaking vacuum, and combining the annealing steps, the patent achieves the contact resistance reduction benefits of a multi-layer structure while minimizing the increase in manufacturing complexity. The merged process maintains relative simplicity compared to alternative approaches that would require separate processing campaigns.
Solution Approach 2:
The patent employs composite materials (MoSi and TiSi) that can be deposited using standard semiconductor manufacturing techniques. The composite structure leverages the complementary properties of both materials to achieve superior contact resistance reduction, while the deposition processes for each layer are compatible with existing manufacturing equipment and protocols, thereby maintaining ease of manufacture despite the enhanced material complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integration of MoSi and TiSi significantly reduces contact resistance in both NMOS and PMOS transistors, achieving lower contact resistance than using either metal silicide alone, thereby enhancing transistor performance and drive current.
Implementation Method 1
Integrating molybdenum silicide (MoSi) with titanium silicide (TiSi) layers on both n and p transistors... The integration of MoSi and TiSi significantly reduces contact resistance in both NMOS and PMOS transistors, achieving lower contact resistance than using either metal silicide alone
Implementation Method 2
optionally, in-situ annealing the substrate in an atmosphere of hydrogen (H2)
Data Source
AI summary
Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor. The substrate is pre-cleaned. A molybdenum silicide (MoSi) layer is deposited on one or more of the p transistor and the n transistor. A titanium silicide (TiSi) layer is formed on the n transistor and the p transistor. A capping layer may be formed on the titanium silicide (TiSi) layer. The method may be an integrated method performed in a processing chamber without breaking vacuum.