Motherboard Signal Noise Reduction via Layer Segmentation
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Solution Overview
Problem
Signal transmission between different layers in a multilayer motherboard is affected by long distances and connecting interfaces, leading to noise and compatibility issues, especially for high-frequency signals between the CPU and memory slots.
Innovation Solution
The motherboard design includes a multilayer printed circuit board with the CPU slot on one wiring layer and memory slots on the same layer, with first and second traces on different layers, electrically connected through vias, minimizing routing changes between layers to reduce signal noise and compatibility issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If signals are transmitted between different layers using multiple connecting interfaces, then the motherboard can provide sufficient wiring area and component mounting space, but signal noise and transmission errors increase especially for high-frequency signals
Solution Approach 1:
The patent segments the signal transmission paths by assigning different layers to different functions: the first wiring layer handles CPU-to-memory connections while the second wiring layer handles other signals. This segmentation reduces the number of interfaces high-frequency signals must cross, thereby reducing noise while maintaining sufficient wiring area through the multilayer structure.
Solution Approach 2:
The patent applies local quality by giving different layers different functional characteristics. The first wiring layer is optimized for CPU connections with direct traces, while the second wiring layer handles other signals. This local optimization ensures that high-frequency signals experience minimal noise by being routed through the most suitable layer.
2Adaptability or versatility
If multiple connecting interfaces are used between different layers, then the motherboard can accommodate more components and provide sufficient routing space, but compatibility issues and transmission errors increase
Solution Approach 1:
The patent segments signal transmission into distinct layer-specific paths. The first wiring layer is dedicated to CPU-to-memory connections with direct traces, while the second wiring layer handles other signals. This segmentation maintains compatibility by reducing interface complexity for critical high-frequency signals while still allowing component mounting flexibility through the multilayer structure.
Solution Approach 2:
The patent applies local quality by optimizing specific layers for specific functions. The first wiring layer is locally optimized for CPU connections with minimal interfaces, while the second wiring layer handles other signals. This local optimization improves reliability for critical signals without sacrificing overall system versatility.
3Area of stationary object
If long transmitting distances and multiple connecting interfaces are used, then the motherboard can provide sufficient wiring area, but signal transmission quality deteriorates for high-frequency signals
Solution Approach 1:
The patent segments the wiring structure into functionally distinct layers. The first wiring layer handles CPU-to-memory connections with direct traces, minimizing transmission distance and interfaces. The second wiring layer handles other signals. This segmentation maintains sufficient wiring area while improving signal transmission quality by reducing the number of interfaces high-frequency signals must cross.
Solution Approach 2:
The patent applies local quality by optimizing the first wiring layer specifically for CPU connections with minimal interfaces and direct traces. This local optimization ensures high signal transmission quality for critical high-frequency signals while the overall multilayer structure provides sufficient wiring area through the second wiring layer for other components.
Data Source
AI summary
A motherboard includes a multilayer printed circuit board (PCB), a central processing unit (CPU) slot, at least one first memory slot, at least one second memory slot, a plurality of first traces, and a plurality of second traces. The CPU slot, the first memory slot, and the second memory slot are disposed on the first wiring layer of the multilayer PCB, and the second memory slot is disposed between the first memory slot and the CPU slot. The first traces are disposed on the first wiring layer of the multilayer PCB. The CPU slot is electrically connected to the first memory slot by the first traces. The second traces are disposed on the second wiring layer of the multilayer PCB which is different from the first wiring layer, and the CPU slot is electrically connected with the second memory slot by the second traces.