Motherboard Memory Buffer Topology for More DIMMs Per Channel
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Solution Overview
Problem
Existing data storage systems face challenges in scaling memory capacity due to processor cost constraints and limited increases in memory per processor, leading to inefficiencies in handling increased demands.
Innovation Solution
Implementing Smart Memory Cubes (SMCs) with programmable and ASIC memory interfaces that perform application-specific primitive operations, reducing latency by processing commands directly within the memory system, and reusing DIMM buffer chips on the motherboard to increase the number of DIMMs per channel, thereby enhancing memory capacity and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If processors are added to increase memory capacity, then memory capacity is improved, but processor cost increases
Solution Approach 1:
The patent extracts the memory interface functionality from the processor and places it in a separate memory interface device. This allows memory capacity to be scaled independently from processor cost, as the memory interface can be optimized and reused across multiple processors without requiring each processor to have full memory interface capabilities.
Solution Approach 2:
The memory interface device serves multiple processors simultaneously, providing a universal interface solution that reduces the need for dedicated high-cost memory interfaces in each processor. This multi-functional approach allows cost-effective scaling of memory capacity across the system.
2Quantity of substance
If memory per processor is increased, then memory capacity is improved, but memory bandwidth becomes insufficient
Solution Approach 1:
The patent segments the memory system into multiple independent memory channels, each with dedicated bandwidth. This allows memory capacity to be increased by adding more channels while maintaining adequate bandwidth through parallel data paths, preventing bandwidth bottlenecking as capacity scales.
Solution Approach 2:
The patent introduces additional dimensional scaling by adding more memory channels and DIMMs per channel, rather than simply increasing memory per processor in a single dimension. This multi-dimensional approach allows capacity and bandwidth to scale together by utilizing parallel channels.
3Quantity of substance
If the number of DIMMs per channel is increased, then memory capacity is improved, but signal integrity deteriorates
Solution Approach 1:
The patent introduces buffer chips as intermediary devices between the memory controller and DIMMs. These buffers act as signal repeaters and conditioners, maintaining signal integrity even when the number of DIMMs per channel is increased. The buffers regenerate and retime signals, preventing degradation as more DIMMs are added to each channel.
4Quantity of substance
If processors are scaled to meet memory demands, then memory capacity is improved, but system complexity increases
Solution Approach 1:
The patent extracts memory interface functionality from the processor into a dedicated memory interface device. This separation reduces processor complexity and allows memory capacity to be scaled independently, as the interface logic is externalized and can be optimized separately from the processing units.
Solution Approach 2:
The memory interface device serves as an intermediary layer between processors and memory, simplifying the overall system architecture. This intermediary handles the complexity of memory management, signal conditioning, and channel coordination, allowing processors to remain simpler while still supporting large memory capacities.
Data Source
AI summary
A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.