Motion Compensation Circuit Segmentation for Video Decoding
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Solution Overview
Problem
Video decoding systems face complexity in designing motion compensation circuits for variable macroblock sizes in H.264 and VC-1 standards, leading to inefficiencies and high CPU burden, especially for high-definition decoding with low-frequency and low-power CPUs.
Innovation Solution
An electronic device with a processing unit and a motion compensation acceleration circuit that collaboratively perform motion compensation, where the processing unit handles smaller macroblocks and the acceleration circuit handles larger ones, reducing design complexity and CPU burden by distributing interpolation and reconstruction tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a motion compensation circuit is designed to handle variable macroblock sizes in H.264 and VC-1 standards, then the system can decode video streams according to standard requirements, but the design complexity of the motion compensation circuit increases significantly
Solution Approach 1:
The patent divides the motion compensation task into two segments: the processing unit handles decoding and generates interpolation values for all macroblocks, while the motion compensation acceleration circuit only performs motion compensation for macroblocks of size 16x16 or larger. This segmentation allows the hardware circuit to be simplified while maintaining support for variable macroblock sizes through software-hardware collaboration.
2Adaptability or versatility
If only a CPU is used for decoding video bitstreams with high definition, then the system can handle variable macroblock sizes flexibly, but the CPU becomes burdened and requires high frequency and power consumption
Solution Approach 1:
The patent segments the decoding workload between software (processing unit) and hardware (acceleration circuit). The processing unit handles macroblocks smaller than 16x16, while the hardware acceleration circuit handles 16x16 and larger macroblocks. This division reduces the burden on the CPU, allowing it to operate at lower frequencies and power consumption while maintaining flexibility.
Solution Approach 2:
The patent introduces an intermediate structure (motion compensation acceleration circuit) that mediates between the CPU and the motion compensation process. The CPU generates interpolation values and controls the hardware circuit, which then performs the computationally intensive motion compensation operations, reducing the CPU's direct involvement in heavy calculations.
3Productivity
If a motion compensation acceleration circuit is designed to handle all macroblock sizes, then the hardware can process all cases, but the circuit complexity increases and requires more hardware resources
Solution Approach 1:
The patent segments the processing responsibilities so that the motion compensation acceleration circuit only handles macroblocks of size 16x16 or larger, while smaller macroblocks are processed by the software-based processing unit. This segmentation allows the hardware circuit to be optimized for specific cases rather than needing to handle all possible macroblock sizes, reducing hardware complexity.
Data Source
AI summary
An electronic device for motion compensation is provided. The electronic device has a processing unit configured to perform a decoding program on a video bitstream to output decoding data, wherein the decoding data has a plurality of inter-prediction macroblocks, and the processing unit further generates a plurality of first pixel interpolation values according to the inter-prediction macroblocks which are smaller than a predetermined macroblock size. A motion compensation acceleration circuit is configured to generate a plurality of second pixel interpolation values according to the inter-prediction macroblocks which are larger than or equal to the predetermined macroblocks size, and generate a plurality of reconstructed macroblocks according to the first pixel interpolation values, the second pixel interpolation values, and a plurality of corresponding residue values.