Motion Estimation Circuit Design for Reduced Area
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Solution Overview
Problem
Conventional motion estimation (ME) and motion compensation (MC) algorithms are math-heavy and impractical for real-time software implementation due to large circuit area requirements, making them unsuitable for cost-effective hardware implementation.
Innovation Solution
A circuit design that includes reduced memory and register sizes, along with a metric circuit for block-matching metric calculation and pixel shifting, eliminates the need for extensive multiplexers, reducing the circuit area and wiring complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional ME/MC algorithms are implemented in hardware circuit, then real-time processing is achieved, but circuit area becomes too tremendous
Solution Approach 1:
The patent divides the large search range into multiple smaller sub-search ranges, each stored in separate memory blocks. Instead of loading the entire search range at once, the circuit processes one sub-range at a time, significantly reducing the memory size and circuit area required while maintaining real-time processing capability.
Solution Approach 2:
The patent pre-organizes the search range data into structured memory formats with predetermined row and column arrangements. This preliminary organization allows the metric circuit to efficiently access and process only the necessary data blocks without requiring large buffers or complex data management circuits, thereby reducing overall circuit area.
2Adaptability or versatility
If conventional ME/MC algorithms are implemented in software, then flexibility is maintained, but real-time processing cannot be achieved
Solution Approach 1:
The patent replaces software-based iterative computation with a dedicated hardware circuit that performs block-matching metric calculations through specialized metric circuits. This hardware implementation maintains algorithmic flexibility through configurable memory structures while achieving real-time processing speeds unattainable by software execution.
3Speed
If full search range is loaded into registers, then processing speed is improved, but register size and wiring complexity increase
Solution Approach 1:
The patent segments the full search range into multiple smaller sub-ranges that can be loaded into registers simultaneously. This segmentation allows the use of smaller, manageable register sizes with correspondingly reduced wiring complexity, while the systematic processing of multiple sub-ranges maintains overall processing speed.
Data Source
AI summary
Circuits for performing motion estimation (ME) and motion compensation (MC) are disclosed. In the ME circuit, rows of a first register are correspondingly coupled to rows of a first memory that stores a search range of a first frame, and rows of a second register are correspondingly coupled to rows of a second memory that stores a search range of a second frame. Block-matching metric calculations are performed through the search range to obtain a motion vector (MV). In the MC circuit, first multiplexers couples each row of a first register to corresponding row of a first memory, and each macro block (MB) may accordingly be selected from the first memory and loaded into the first register. Second multiplexers couples each row of a second register to corresponding row of a second memory, and each MB may accordingly be selected from the second memory and loaded into the second register.