Motion Estimation SSD Calculation via B(B-2A) Subtraction
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Solution Overview
Problem
Current motion estimation methods for video compression, such as sum-of-square differences (SSD), are computationally intensive and resource costly, particularly in FPGA implementations, due to the need for complex multiplier stages and high calculation loads, especially for high-definition video at 30 frames per second.
Innovation Solution
A method and integrated circuit architecture that uses a digital signal processing block with a subtractor, multiplier, and adder to perform the SSD calculation efficiently by simplifying the SSD equation to reduce the need for complex multiplication, utilizing the equation B(B−2A) to indicate the difference between reference and predicted frames, and propagating carry data through an array of digital signal processing blocks to compute the Sum of Square Differences-based result.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sum-of-square differences (SSD) motion estimation is used to achieve high-quality motion estimation, then measurement precision is improved, but device complexity and computational overhead increase significantly
Solution Approach 1:
The patent segments the SSD calculation into multiple processing stages: obtaining reference and predicted pixel values, calculating squared differences, summing the squared differences, and comparing with threshold values. This segmentation allows each stage to be processed independently and efficiently, reducing the need for complex multiplier stages while maintaining SSD-quality motion estimation.
Solution Approach 2:
The patent changes the computational parameters by using simplified calculation methods for SSD. Instead of requiring complex multiplication operations, the patent uses alternative computational approaches that achieve the same motion estimation quality with reduced device complexity, particularly reducing the number and complexity of multiplier stages required in FPGA implementations.
2Measurement precision
If SSD motion estimation is implemented for high-definition video at 30 frames per second, then measurement precision is improved, but productivity decreases due to high calculation loads
Solution Approach 1:
The patent performs preliminary actions by pre-calculating and storing reference frame data, and by preparing prediction data before the actual SSD calculation. This allows the motion estimation process to proceed more efficiently during video encoding, enabling high-definition video processing at 30 frames per second without sacrificing motion estimation quality.
Solution Approach 2:
The patent implements partial SSD calculation by using simplified computation methods that calculate only the necessary components for motion estimation. This partial action approach reduces the overall calculation load while maintaining sufficient precision for high-definition video processing at high frame rates.
3Measurement precision
If complex multiplier stages are used for SSD calculation, then measurement precision is improved, but use of energy increases
Solution Approach 1:
The patent extracts and removes the complex multiplier stages from the SSD calculation process. By taking out these energy-intensive components and replacing them with simpler computational operations, the patent maintains SSD calculation accuracy while significantly reducing energy consumption in FPGA and integrated circuit implementations.
Data Source
AI summary
Motion estimation is described. A first portion of a predicted frame is obtained. The first portion is for a first predicted value. A first subset of a reference frame is obtained. The first subset is for a first reference value. Twice the first predicted value is subtracted from the first reference value. The outcome of the subtracting is multiplied by the first reference value to produce a partial result. The partial result is used for indication of a degree of difference between the first portion and the first subset.