Decoder-Side Motion Refinement With Reference Block Prefetch

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Solution Overview

Problem

Video coding systems face high memory-access latency due to the time-consuming process of fetching reference blocks from off-chip memory for decoder-side motion estimation and compensation, which hinders high-throughput decoder implementations.

Innovation Solution

Implement a two-pass motion-data reconstruction process, decoupling decoder-side motion estimation from direct memory access by using a coarse motion-data reconstruction block to fetch all required reference blocks before decoder-side motion estimation, allowing for pre-fetching and reducing memory latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If reference blocks are fetched from off-chip memory for decoder-side motion estimation and compensation, then motion compensation can be performed, but memory-access latency increases

Engineering Contradiction:
Improvemotion compensation accuracyVSAvoidmemory-access latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing a first pass of motion-data reconstruction to obtain coarse motion vectors before the actual decoder-side motion estimation. This allows the system to pre-identify and prefetch reference blocks to an on-chip buffer before they are needed for the second pass motion estimation, thereby eliminating memory-access latency during the critical computation phase.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If decoder-side motion estimation is performed, then motion vector accuracy is improved, but processing time increases due to sequential operations

Engineering Contradiction:
Improvemotion vector accuracyVSAvoiddecoder throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent segments the motion-data reconstruction process into two distinct passes: a first pass that generates coarse motion vectors and identifies reference block locations, and a second pass that performs precise decoder-side motion estimation. This segmentation allows the first pass to prepare data in advance, enabling the second pass to operate with higher accuracy without sequential bottlenecks, thereby improving overall decoder throughput.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The first pass of motion-data reconstruction serves as a preliminary action that prepares coarse motion vectors and reference block identifiers before the second pass. This preliminary computation enables the system to prefetch necessary data and organize it in on-chip buffers, allowing the second pass to execute faster with improved accuracy without creating sequential dependencies that would reduce throughput.

Inventive Principle:
Principle #10Preliminary action

3Loss of time

If all reference blocks are pre-fetched before decoder-side motion estimation, then memory latency is reduced, but memory bandwidth consumption increases

Engineering Contradiction:
Improvememory latencyVSAvoidmemory bandwidth requirements
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent uses preliminary action by performing motion-data reconstruction in a first pass to obtain coarse motion vectors and identify specific reference block locations. This identification step enables selective prefetching of only the necessary reference blocks to on-chip buffers before the second pass motion estimation, rather than fetching all possible reference blocks. This approach reduces memory latency while controlling memory bandwidth consumption through targeted data retrieval.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20260101059A1Memory latency management for decoder-side motion refinement
Publication Date: 2026.04.09 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US20260101059A1 patent drawing
  • US20260101059A1 patent drawing
  • US20260101059A1 patent drawing

AI summary

A system includes memory and at least one processor coupled to the memory. The processor processes a received bitstream to generate quantized data and control data. The process also generates decoded motion data based on a portion of the control data, fetches one or more reference blocks associated with a current prediction unit of a decoder pipeline region based on the decoded motion data and generates refined motion data based on the decoded motion data and the one or more reference blocks. The processor further generates one or more inter-prediction blocks based on the refined motion data and the one or more reference blocks by performing a motion compensation operation.