Scalable Motion Search Hardware Assist Unit for Array Processor
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current processor architectures are inadequate to efficiently handle the high computational demands of motion estimation/compensation for high definition video encoding, particularly due to the high computational intensity and memory requirements, which limits their ability to support multiple video standards in a cost-effective manner.
Innovation Solution
A scalable motion search hardware assist unit is integrated into a SIMD array processor, featuring multiple independent arithmetic pipelines and a local memory interface, allowing for efficient motion estimation by processing macro blocks and search windows in parallel, thereby reducing the computational burden on processing elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a processor is designed to meet the computational requirements of motion estimation for HD video encoding, then the processing speed and computational capability are improved, but the device complexity and manufacturing cost increase significantly
Solution Approach 1:
The processor is divided into multiple independent processing elements (PEs) organized in a two-dimensional array, where each PE can independently execute instructions and process video data. This segmentation allows the system to achieve high computational throughput for motion estimation by parallelizing operations across multiple PEs, while each individual PE maintains relatively simple architecture that is cost-effective to manufacture.
Solution Approach 2:
The processor introduces a third dimension to the traditional von Neumann architecture by adding a spatial dimension with multiple PEs arranged in a two-dimensional array. Each PE has its own local memory and can operate independently, transforming the single-processor sequential architecture into a multi-processor parallel architecture. This dimensional expansion enables simultaneous execution of multiple motion estimation operations, significantly improving processing speed without requiring each PE to be overly complex.
2Adaptability or versatility
If multiple video encoding standards are supported, then the adaptability and versatility are improved, but the device complexity and computational requirements increase
Solution Approach 1:
Each processing element is designed as a universal unit capable of executing multiple video encoding algorithms and supporting different video standards (MPEG-2, H.264, VC-1, etc.). The PEs can be dynamically configured through software to perform different functions such as motion estimation, deblocking filtering, and other encoding operations. This universality allows a single processor architecture to support multiple video standards without requiring separate dedicated hardware for each standard, thereby improving adaptability while controlling device complexity.
3Productivity
If parallel processing is increased to meet computational demands, then the productivity is improved, but the memory bandwidth requirements and data processing intensity increase
Solution Approach 1:
Local memory is extracted and attached directly to each processing element, creating a distributed memory architecture where each PE has its own private memory space. This extraction of memory from the centralized system and placement at the edge of each PE reduces the memory bandwidth burden on the central memory interface. Each PE can access its local memory independently without contending for bandwidth with other PEs, enabling high parallel computational throughput while managing memory bandwidth requirements efficiently.
Data Source
AI summary
An apparatus is described for attaching a motion search hardware assist unit to a processing element and its local memory. A current macro block storage unit is attached to a local memory interface unit for storage of a copy of a current macro block from the local memory. A search window reference storage unit having N rows is attached to a local memory interface unit for storage of a copy of N rows of pixels from a search window from the local memory. N independent arithmetic pipelines are attached to the current macro block storage unit and the search window reference storage. Each pipeline operates on one of the N rows of the search window reference storage unit and a corresponding row of the current macro block of the current macro block storage unit. An accumulator is attached to the N independent pipelines to accumulate results from the N arithmetic pipelines, to produce independent results for different organizations of macro blocks.