Motor Control Circuit Gain Adjustment via Segmented Error Detection
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Solution Overview
Problem
Existing motor control circuits face limitations in adjusting gains over a broad control range due to the use of digital multiplying devices, which result in complex circuits, slow calculation speeds, and challenges in miniaturization and precision of rotation driving control.
Innovation Solution
A motor control circuit is designed with a simple digital circuit that includes speed and phase error detecting sections, using adjustable reference clocks to generate torque command data and control motor driving, allowing for independent gain adjustments without influencing PWM duty ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If digital multiplying devices are used to adjust gains in motor control circuits, then gain adjustment capability is improved, but circuit complexity increases and calculation speed decreases
Solution Approach 1:
The patent segments the gain adjustment function into separate speed error detecting section and phase error detecting section, each with independent counters and latch circuits. This segmentation allows gain adjustment without requiring complex digital multiplying devices, thereby reducing circuit complexity while maintaining adaptability.
Solution Approach 2:
The patent replaces the digital multiplying device (electronic calculation system) with a counter-based detection system using reference clocks. This substitution achieves gain adjustment through counting operations rather than multiplication, simplifying the circuit while preserving functionality.
2Measurement precision
If digital multiplying devices are used for gain adjustment, then gain control precision is improved, but calculation speed decreases
Solution Approach 1:
The patent uses latch circuits to capture and hold the count values from the counters at specific timing points (when speed or phase pulses are detected). This preliminary action of storing count values allows subsequent gain calculation to be performed quickly without requiring complex real-time multiplication operations, thus improving calculation speed while maintaining precision.
Solution Approach 2:
The patent substitutes digital multiplication operations with counter-based detection and comparison operations. The counters accumulate reference clock cycles, and the latch circuits capture these counts for comparison with target values, achieving precise control through counting rather than multiplication, which significantly improves calculation speed.
3Adaptability or versatility
If reference clock frequency is changed to adjust PWM gain, then gain adjustment is achieved, but PWM duty ratio stability is affected
Solution Approach 1:
The patent separates the gain adjustment function from the PWM generation function by using independent counters for speed and phase error detection. The PWM duty ratio is determined separately based on the detected errors and target values, allowing gain adjustment through counter configuration without affecting PWM stability.
Solution Approach 2:
The patent introduces latch circuits as intermediaries between the counter detection system and the PWM control system. These latch circuits capture and hold the count values, providing a stable intermediate representation that decouples the gain adjustment mechanism from the PWM duty ratio generation, thereby maintaining PWM stability while enabling gain flexibility.
Data Source
AI summary
A motor control circuit for a motor is provided. The motor control circuit drives the motor based on torque command data. The torque command data is output by adding speed error data output from a speed error detecting section based on a first reference clock and a speed pulse and phase error data output from a phase error detecting section based on a second reference clock and the speed pulse. Each of the speed error data and the phase error data is output within a detection range set by a setting section provided for each of the speed error detecting section and the phase error detecting section.