Motor Drive FET Layout for Latch-Up Suppression in Compact Mounting
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Solution Overview
Problem
Existing motor drive circuits face issues with latch-up effects during current disconnection, which are exacerbated by increased mounting area requirements in countermeasures to prevent latch-up, leading to inefficiencies.
Innovation Solution
The motor drive circuit incorporates a specific layout design where the first phase low-side FET is disposed between the first phase high-side FET and the second phase low-side FET, and the second phase high-side FET is disposed between the second phase low-side FET and the first phase high-side FET, reducing parasitic transistor gains and minimizing mounting area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If countermeasures such as enlarging inter-element distance, burying element isolation portions, or forming floating structures are adopted to eliminate the latch-up effect, then the latch-up effect is suppressed, but the mounting area increases
Solution Approach 1:
A third FET is introduced as an intermediary element positioned between the first-phase low-side FET and the second-phase high-side FET. This third FET acts as a buffer that disrupts the parasitic transistor conduction path, preventing latch-up effects without requiring increased spacing or isolation structures between the original FETs.
Solution Approach 2:
The output stage is segmented by introducing an additional FET that divides the original FET arrangement into distinct functional zones. This segmentation breaks the direct interaction between complementary FETs of different phases, eliminating the latch-up pathway while maintaining compact layout.
2Area of stationary object
If the mounting area is reduced by compact layout, then space efficiency is improved, but the latch-up effect occurs unexpectedly during current disconnection
Solution Approach 1:
The third FET serves as a protective intermediary that enables compact layout while preventing latch-up. By positioning this intermediary FET between critical complementary FET pairs, the design achieves both space efficiency and reliability without requiring large inter-element distances.
Solution Approach 2:
The third FET is pre-positioned in the layout to proactively prevent latch-up conditions before they can occur during current disconnection. This preliminary structural arrangement ensures that even in compact configurations, the parasitic transistor conduction paths are blocked in advance.
Data Source
AI summary
The present disclosure provides a motor drive circuit. The motor drive circuit includes a first-phase half bridge circuit and a second-phase half bridge circuit. The first and second phase half bridge circuits include first-phase and second-phase high-side FETs and first-phase and second-phase low-side FETs. The first-phase and second-phase high-side FETs are configured to apply a first voltage to a first end. A second end of the first-phase and second-phase high-side FETs is connected to the first end. A second voltage lower than the first voltage is applied to the second end. The first-phase low-side FET or the second-phase high-side FET is disposed between the first-phase high-side FET and the second-phase low-side FET. The second-phase low-side FET or the first-phase high-side FET is disposed between the first-phase low-side FET and the second-phase high-side FET.