Motor Driver Bridge Circuit with Adjustable Dead Time Control

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Solution Overview

Problem

Existing bridge circuits in motor driver apparatuses face challenges in optimizing dead time to avoid through current, as the optimal dead time varies with motor characteristics and manufacturing variations, leading to inefficiencies and potential torque reduction.

Innovation Solution

A circuit device with a bridge circuit, delay circuits, and a control circuit that allows for variable setting of delay times in a register, enabling independent adjustment of delay times for transistors to minimize through current by delaying driving pulse signals, thereby optimizing dead time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed dead time is provided in the bridge circuit to avoid through current, then through current is prevented, but the system cannot adapt to different motor characteristics and manufacturing variations, leading to suboptimal performance

Engineering Contradiction:
Improvethrough current preventionVSAvoidadaptability to different motor characteristics
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies dynamics by making the dead time adjustable rather than fixed. The delay setting register allows the dead time to be dynamically changed according to different motor characteristics and manufacturing variations, enabling the system to adapt to various conditions while maintaining reliable through current prevention.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of dead time from a fixed value to a variable that can be adjusted through the delay setting register. This parameter change enables the bridge circuit to optimize dead time for different motor types and manufacturing variations, resolving the contradiction between reliability and adaptability.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a longer dead time is provided to ensure transistors are not simultaneously on, then through current is avoided, but power inefficiency and torque reduction increase

Engineering Contradiction:
Improvethrough current avoidanceVSAvoidpower inefficiency
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent uses dynamics to adjust the dead time duration based on actual transistor switching characteristics. By making the dead time configurable through the delay setting register, the system can use the minimum necessary dead time to prevent through current, thereby reducing power inefficiency and torque loss while maintaining reliability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent enables self-service by allowing the delay setting register to be configured with optimal dead time values specific to each application. This self-configuration capability enables the system to automatically optimize the balance between through current prevention and energy efficiency without requiring excessive dead time.

Inventive Principle:
Principle #25Self-service

3Reliability

If delay time is increased to prevent simultaneous transistor on-state, then through current is prevented, but the switching response time and overall system performance decrease

Engineering Contradiction:
Improvesimultaneous on-state preventionVSAvoidswitching response time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the delay time adjustable through the delay setting register. This allows the system to use the minimum necessary delay to prevent simultaneous transistor on-state, thereby maintaining reliability while minimizing the loss of switching response time and preserving overall system performance.

Inventive Principle:
Principle #15Dynamics

4Productivity

If individual delay times for high-side and low-side transistors are adjusted, then optimal dead time can be achieved, but the device complexity increases due to additional delay setting registers and delay circuits

Engineering Contradiction:
Improveoptimal dead time achievementVSAvoidcomplexity of delay setting register and delay circuits
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the delay control into separate delay setting registers and delay circuits for each transistor. This segmentation allows independent optimization of delay times for high-side and low-side transistors, achieving optimal dead time while organizing the complexity into manageable, modular components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses local quality by allowing different delay times to be set for different transistors through individual delay setting registers. This enables each transistor to have its own optimized delay characteristic, achieving optimal overall dead time while managing device complexity through localized control.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20150097599A1Circuit device and electronic device
Publication Date: 2015.04.09 SEIKO EPSON CORP
  • US20150097599A1 patent drawing
  • US20150097599A1 patent drawing
  • US20150097599A1 patent drawing

AI summary

The invention provides a motor driver including pre-drivers for a bridge circuit, delay circuits, and a delay setting register, wherein in order to suppress short-circuit current caused at the time of signal switching in the bridge circuit, the delay circuits are set based on delay time information in the delay setting register so as to control signals input into the pre-drivers. The signals input into the individual pre-drivers are delayed differently by the delay circuits based on the delay time information in the delay setting register, thereby preventing a short-circuit current flow caused by an offset in the timing of the individual pre-drivers being turned on and off.