Motor Driver Circuit for Stable FG Signal During Startup
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Solution Overview
Problem
Existing motor driver circuits face challenges in generating a stable frequency generation (FG) signal during motor startup, particularly when the motor is stopped or idling, due to noise and flutter in the Hall signal, which affects synchronization and rotation speed control.
Innovation Solution
A motor driver circuit with a control logic circuit that generates an energization pattern for compulsory synchronous drive, switching between high and low detection periods, sets an internal Hall signal based on detected levels, and produces an FG signal using this internal signal to remove noise and ensure correct synchronization with the rotor's rotation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the motor driver circuit uses the Hall signal directly for FG signal generation during motor startup, then the circuit operation is simplified, but the FG signal becomes unstable due to noise and flutter in the Hall signal
Solution Approach 1:
An internal Hall signal is introduced as an intermediary between the external Hall signal and the FG signal generation. The internal Hall signal is set based on the external Hall signal level during specific detection periods (high detection period or low detection period), filtering out noise and flutter while preserving the essential synchronization information needed for stable FG signal generation.
Solution Approach 2:
The control logic circuit performs preliminary action by pre-setting the internal Hall signal level during designated detection periods before using it for FG signal generation. This preliminary setting during high detection period or low detection period ensures that the signal used for FG generation is already filtered and stable, preventing noise and flutter from affecting the final output.
2Device complexity
If the motor driver circuit switches driving phase at predetermined time internal according to predetermined sequence (compulsory synchronous drive), then the control is simplified, but the synchronization with rotor position becomes inaccurate when motor is stopped or idling
Solution Approach 1:
The control logic circuit dynamically switches between two operating modes: compulsory synchronous drive mode (switching driving phase at predetermined time internal according to predetermined sequence) and Hall signal synchronization mode (switching based on detected Hall signal level). This dynamic adaptation allows the system to use the simpler compulsory synchronous drive when appropriate while achieving accurate rotor position synchronization when the motor is stopped or idling by transitioning to Hall signal-based control during high detection period or low detection period.
Data Source
AI summary
The present disclosure provides a control logic circuit. The control logic circuit controls an inverter circuit connected to a motor based on Hall signal. The control logic circuit generates an energization pattern for a compulsory synchronous drive, and switches between a high detection period and a low detection period in accordance with the energization pattern. The control logic circuit sets an internal Hall signal as high when a high level of the Hall signal is detected during the high detection period and sets the internal Hall signal as low when a low level of the Hall signal is detected during the low detection period. Therefore, the control logic circuit generates an FG signal according to the internal hall signal.