Motor Driving Circuit Pulse Width Modulation Sub-pulse Segmentation
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Solution Overview
Problem
Existing motor driving techniques face challenges in generating a pulse signal with a short cycle while minimizing the increase in clock signal frequency, which affects driving efficiency and is difficult to implement due to circuit area restrictions.
Innovation Solution
A motor driving circuit that generates a pulse signal with a reduced apparent cycle by creating multiple sub-pulses with an average duty ratio set according to the error signal, allowing for a higher apparent frequency without increasing the clock signal frequency, and is monolithically integrated on a semiconductor substrate to reduce circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the cycle of the pulse-width modulation signal is shortened to improve driving efficiency, then the driving efficiency is improved, but the frequency of the clock signal must be increased which increases noise and circuit area
Solution Approach 1:
The pulse signal is divided into multiple continuous sub-pulses instead of using a single pulse. By segmenting one pulse into k sub-pulses, the apparent cycle is reduced by a factor of k while maintaining the same clock signal frequency, thus improving driving efficiency without increasing clock frequency or circuit area
Solution Approach 2:
The invention uses periodic sub-pulses with a shorter apparent cycle to achieve higher driving efficiency. The sub-pulses are generated periodically with k times the frequency of the original pulse signal, creating an effective high-frequency drive without requiring a high-frequency clock signal
2Speed
If the frequency of the clock signal is increased to generate a pulse signal with short cycle, then the cycle of the pulse signal is shortened, but the clock signal noise increases and circuit area increases
Solution Approach 1:
The single high-frequency pulse is segmented into multiple continuous sub-pulses. This allows the system to achieve a short apparent pulse cycle (high speed) by using multiple lower-frequency sub-pulses instead of a single high-frequency pulse, thereby reducing clock signal noise while maintaining fast response
3Speed
If the frequency of the clock signal is increased to generate a pulse signal with short cycle, then the cycle of the pulse signal is shortened, but the circuit area increases due to oscillator requirements
Solution Approach 1:
By segmenting the pulse into multiple sub-pulses, the system achieves a short apparent cycle without requiring a high-frequency oscillator. The sub-pulse generation uses the existing clock signal with a lower frequency, eliminating the need for additional high-frequency oscillator circuits and reducing overall circuit area
Solution Approach 2:
The existing clock signal and pulse modulator are made multi-functional by configuring them to generate multiple sub-pulses. This universal approach allows the same circuit components to achieve both short pulse cycles and low noise without requiring separate high-frequency oscillator circuits
Data Source
AI summary
When the bit number of an error signal ERR2 is n and the magnitude of the error signal ERR2 is “a” (a is an integer) in decimal notation, a pulse-width modulator generates a PWM signal Spwm as a set of k (k is an integer of 2 or more) continuous sub-pulses. Further, the pulse-width modulator generates k sub-pulses in such a manner that the average value of the duty ratios of the sub-pulses becomes approximately a/2n.