Motor Driving Apparatus Phase Error Compensation for Jitter Reduction
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Solution Overview
Problem
In motor systems, such as hard disk drives, rotational jitter is increased due to manufacturing variations like magnetic pole position and stator mounting variations, leading to errors in conduction timing via PLL control, which affects motor position detection accuracy and recording density.
Innovation Solution
A motor driving apparatus with a phase error detecting unit, compensator, and conduction timing generating unit synchronizes the detected rotational phase with a targeted phase, using a plurality of registers to store state variables and update operation amounts to minimize phase errors across multiple detection timings within a mechanical angular cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If PLL control is used to generate conduction timing synchronized with back electromotive force, then conduction timing synchronization is improved, but manufacturing variations (magnetic pole position, stator mounting) cause detection timing variations that increase rotational jitter
Solution Approach 1:
The patent implements feedback control by detecting the actual conduction timing, comparing it with the target timing, and adjusting the PLL control parameters based on the detected phase error. This closed-loop feedback mechanism compensates for detection timing variations caused by manufacturing variations, thereby reducing rotational jitter while maintaining conduction timing synchronization.
Solution Approach 2:
The patent changes the operating parameters of the PLL control by adjusting the masking period duration and the detection timing based on detected phase errors. By dynamically modifying these parameters, the system adapts to manufacturing variations and optimizes both conduction timing synchronization and rotational jitter reduction.
2Measurement precision
If masking period is provided to detect zero crossing timing of back electromotive force, then position detection accuracy is improved, but detection timing variations occur due to magnetization variations
Solution Approach 1:
The patent applies preliminary compensation by detecting phase errors in advance and adjusting the masking period timing before the next detection cycle. This preliminary action prevents detection timing variations from accumulating, maintaining position detection accuracy despite magnetization variations in the motor.
3Measurement precision
If multiple detection timings are used within mechanical angle cycle, then conduction timing synchronization is improved, but complexity of control increases
Solution Approach 1:
The patent segments the mechanical angle cycle into multiple detection regions, each with optimized detection timing. By dividing the control cycle into segments and applying specific detection strategies to each segment, the system achieves high-precision conduction timing synchronization while managing control complexity through structured segmentation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces rotational jitter even with magnetization variations, enhancing motor position detection accuracy and conduction timing synchronization, thereby improving recording density and motor performance.
Implementation Method 1
The PLL control loop detects the zero crossing timing of the back electromotive force while observing the back electromotive force of a predetermined phase in the masking period
Data Source
AI summary
The phase error detection unit PHED detects the phase error PERR between the phase of the BEMF and the phase of the phase switching signal COMM (masking signal MSK) at each of a plurality of detection timings that become the zero crossing timings of the BEMF in the mechanical angular cycle. The PI compensator PICPa has a plurality of cycle setting registers REGN 0_0 to REGN 3_5 for each of a plurality of detection timings, and while switching the registers for each detection timing, the PI compensator determines the cycle setting value NCNTS for bringing the inputted phase error PERR close to zero by reflecting the previous cycle setting value NCNT stored in the register. The clock generation unit CGEN sequentially controls the phase switching signal COMM based on the cycle setting value NCNTS.