Motor Drive FET Layout for Latch-Up Suppression in Compact Circuits
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Solution Overview
Problem
Existing motor drive circuits face issues with latch-up effects during current disconnection, which are exacerbated by increased mounting area requirements in countermeasures to prevent these effects.
Innovation Solution
The motor drive circuit employs a layout where the first-phase low-side FET is disposed between the first-phase high-side FET and the second-phase low-side FET, and the second-phase high-side FET is disposed between the second-phase low-side FET and the first-phase high-side FET, reducing parasitic transistor gains and minimizing mounting area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If countermeasures such as enlarging inter-element distance, burying element isolation portions, or forming floating structures are implemented to eliminate the latch-up effect, then the latch-up effect is suppressed, but the mounting area increases
Solution Approach 1:
The patent applies dimensionality change by arranging transistors in a specific spatial configuration where the first-phase low-side transistor or second-phase high-side transistor is disposed between the first-phase high-side transistor and second-phase low-side transistor. This interlaced arrangement in the layout plane reduces parasitic transistor gains without requiring additional isolation structures or increased spacing, thereby suppressing latch-up effects while maintaining compact mounting area.
2Area of stationary object
If the mounting area is reduced by optimizing transistor layout, then space utilization improves, but the latch-up effect may occur during current disconnection
Solution Approach 1:
The patent applies local quality by creating a specific local arrangement pattern where certain transistors (first-phase low-side or second-phase high-side) are positioned between other transistors (first-phase high-side and second-phase low-side). This localized structural configuration reduces parasitic transistor gains in critical areas, effectively suppressing latch-up effects while maintaining overall compactness of the motor drive circuit.
Data Source
AI summary
The present disclosure provides a motor drive circuit. The motor drive circuit includes a first-phase half bridge circuit and a second-phase half bridge circuit. The first and second-phase half bridge circuits include first-phase and second-phase high-side FETs and first-phase and second-phase low-side FETs. The first-phase and second-phase high-side FETs are configured to apply a first voltage to a first end. A second end of the first-phase and second-phase high-side FETs is connected to the first end. A second voltage lower than the first voltage is applied to the second end. The first-phase low-side FET or the second-phase high-side FET is disposed between the first-phase high-side FET and the second-phase low-side FET. The second-phase low-side FET or the first-phase high-side FET is disposed between the first-phase low-side FET and the second-phase high-side FET.