Synchronous Motor Initial Speed Detection via Clarke Current Transform

The patent extracts the speed detection function from the complex high-voltage comparator circuitry and implements it using simple low-voltage logic circuits that can be fabricated using standard low-voltage CMOS processes. The back-emf detection is performed by sampling motor phase currents during high-side switch off-states and processing them through simple digital logic to generate speed estimates, eliminating the need for dedicated high-voltage comparator components.

The patent creates a digital copy of the back-emf signal characteristics by sampling and processing current data through logical operations rather than using analog high-voltage comparators. The speed estimation is derived from counting clock cycles between detected zero-crossing events of the back-emf, replicated through digital logic that mimics the functional behavior of analog comparators without requiring high-voltage analog circuitry.

The patent segments the motor electrical cycle into multiple detectable events by monitoring zero-crossings of back-emf in multiple phases and using logical operations to detect each crossing independently. By counting clock cycles between these segmented detection events and using modular arithmetic, the system achieves position resolution much finer than the traditional 60-degree limit, effectively dividing the measurement resolution into smaller increments.

The patent transitions from direct analog voltage comparison in a single dimension to multi-dimensional digital processing by sampling currents in multiple phases, converting to two-phase currents through coordinate transformation, and processing through multiple logical operations. This dimensional expansion enables finer position resolution by utilizing temporal and logical dimensions rather than relying solely on voltage magnitude comparison.

The patent replaces the mechanical/electrical analog comparator system with a digital logic-based detection system. Instead of using analog high-voltage comparators that require specialized high-voltage fabrication processes, the system uses digital logic circuits operating at low voltages to detect back-emf zero-crossings by sampling and processing current data, enabling standard low-voltage CMOS fabrication while maintaining detection reliability.

The patent changes the operating voltage parameter of the detection system from high-voltage analog operation to low-voltage digital operation. By sampling motor phase currents during high-side switch off-states and processing them through digital logic, the system maintains accurate back-emf detection capability while operating within the voltage range suitable for standard low-voltage wafer fabrication processes.