Motor Speed Controller Phase Difference Detection Segmentation
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Solution Overview
Problem
Existing motor speed control systems using phase-locked loop (PLL) techniques face challenges in precision control due to limited resolution when detecting phase differences, leading to position deviations and synchronization issues, especially when load fluctuations occur.
Innovation Solution
A motor speed controller that includes a reference clock generator, phase reference pulse generator, encoder, edge detector, integer phase difference detector, decimal fraction phase difference detector, mixer, and controller, which generates and combines integer and decimal fraction phase differences to provide continuous and accurate phase difference data for precise motor control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pulse unit detection is used to prevent phase synchronization loss, then reliability is improved, but measurement precision deteriorates due to coarse resolution
Solution Approach 1:
The phase difference detection is segmented into two independent components: an integer phase difference detector that counts complete pulse cycles to prevent synchronization loss, and a decimal fraction phase difference detector that measures sub-pulse phase offsets using a counter and comparator. This segmentation allows each component to specialize in its strength while the combined output achieves both reliability and precision.
Solution Approach 2:
The invention transitions from one-dimensional pulse counting to two-dimensional measurement by adding the decimal fraction component that measures time offsets within a pulse cycle. The phase difference is expressed as a combination of integer cycles and fractional cycles, effectively adding a temporal dimension to the detection resolution.
2Measurement precision
If phase difference detection within 1 pulse cycle is used, then measurement precision is improved, but reliability deteriorates when phase difference exceeds 1 pulse cycle
Solution Approach 1:
The detection system is divided into two segments: the integer phase difference detector handles large phase differences by counting complete pulse cycles, while the decimal fraction phase difference detector handles small phase differences by measuring sub-pulse time offsets. This segmentation eliminates the limitation of detecting only within 1 pulse cycle while maintaining high precision.
Solution Approach 2:
The decimal fraction phase difference detector acts as an intermediary that bridges the gap between integer pulse counting and continuous phase measurement. It measures the residual time offset within a pulse cycle and combines this with the integer count to provide a complete, continuous phase difference measurement that works for both small and large phase differences.
3Device complexity
If only FG pulse detector is used for analog motor control, then device complexity is reduced, but measurement precision deteriorates due to inability to output decimal fraction phase
Solution Approach 1:
The system achieves multi-functionality by making the existing FG pulse detector serve dual purposes: it generates pulse signals for motor control while simultaneously providing timing signals for the decimal fraction phase difference measurement. The counter and comparator circuitry extracts decimal fraction information from the same pulse signal without requiring a separate measurement system.
Solution Approach 2:
The FG pulse signal serves itself by providing both the control function for motor speed regulation and the measurement function for high-resolution phase difference detection. The system uses its own operating pulses to generate the decimal fraction phase information, eliminating the need for external measurement equipment.
Data Source
AI summary
A motor speed controller controls a motor speed to generate a phase reference pulse; generates a FG pulse per rotary angle of the motor; detects a difference between the number of phase reference pulses and the number of FG pulses for output as an integer number phase difference; detects and measures a time difference between an edge of the phase-reference pulse and an edge of the FG pulse in units of the reference clock for output as a decimal fraction phase difference; adds the integer number phase difference to the decimal fraction phase difference at a predetermined ratio for output as a phase difference; and controls driving of the motor in accordance with the phase difference.