Mounting Circuit Substrate Gate Drain Wiring Capacitance

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Solution Overview

Problem

High frequency semiconductor devices experience a decrease in power gain as operating frequency increases, necessitating improvements in mounting circuit substrate design to enhance high frequency characteristics.

Innovation Solution

The mounting circuit substrate incorporates a gate wiring conductor and a drain wiring conductor with a connecting portion that resonates with the LC components of the semiconductor device, increasing capacitance between them to improve power gain characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If conventional mounting circuit substrate configurations are used, then the device can operate at high frequencies, but the power gain decreases as operating frequency increases

Engineering Contradiction:
Improvepower gainVSAvoidoperating frequency
Core Design Contradiction:
PowerVSSpeed

Solution Approach 1:

The patent changes the physical parameters of the wiring conductors by controlling their thickness to specific ranges (gate wiring: 3-7 μm, drain wiring: 3-7 μm) and adjusting their spacing (5-15 μm). These parameter changes optimize the capacitance between conductors to resonate with LC components at high frequencies, thereby maintaining power gain despite increased operating frequency

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent utilizes electrical resonance (analogous to mechanical vibration) by designing the capacitance between gate and drain wiring conductors to resonate with the LC components in the semiconductor device at specific high frequencies. This resonance effect creates a 'hump' in the power gain vs frequency curve, maintaining power gain at operating frequencies where conventional designs would show degradation

Inventive Principle:
Principle #18Mechanical vibration

2Power

If the capacitance between gate and drain wiring conductors is increased to resonate with LC components, then power gain is improved at high frequencies, but the wiring conductor thickness and spacing must be precisely controlled

Engineering Contradiction:
Improvepower gainVSAvoidwiring conductor thickness and spacing control
Core Design Contradiction:
PowerVSManufacturing precision

Solution Approach 1:

The patent specifies concrete parameter ranges for wiring conductor thickness (3-7 μm) and spacing (5-15 μm) that achieve the desired capacitance values. These ranges provide manufacturing tolerances that balance the need for precise capacitance control with practical manufacturing capabilities, ensuring resonance occurs at the target high frequency while accommodating normal fabrication variations

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration results in a power gain vs. frequency curve with a hump at the operating frequency band, maintaining power gain at high frequencies without decreasing it, thus enhancing the high frequency performance of semiconductor devices.

Implementation Method 1

A capacitance between the connecting portion of the gate wiring conductor and the connecting portion of the drain wiring conductor resonates with the LC components in the high frequency semiconductor device

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

A capacitance between the connecting portion of the gate wiring conductor and the connecting portion of the drain wiring conductor resonates with the LC components in the high frequency semiconductor device so that the power gain vs. frequency characteristic curve of the high frequency semiconductor device has a hump at a frequency in the operating frequency band

Methodology Applied
Scientific EffectResonance: Resonance

Data Source

PatentUS8125009B2Mounting circuit substrate
Publication Date: 2012.02.28 MITSUBISHI ELECTRIC CORP
  • US8125009B2 patent drawing
  • US8125009B2 patent drawing
  • US8125009B2 patent drawing

AI summary

A semiconductor package containing a field effect transistor (FET) used in a high frequency band includes a mounting circuit substrate on which the semiconductor device is mounted. The mounting circuit substrate has a gate wiring conductor, a drain wiring conductor, and a source wiring conductor, which are connected to the gate electrode, the drain electrode, and the source electrode, respectively, of the semiconductor device. The gate wiring conductor and the drain wiring conductor extend toward each other so that their adjacent or facing ends are in close proximity to each other, thereby increasing the capacitance between the gate wiring conductor and the drain wiring conductor.