Semiconductor Mounting Substrate Insulation for Crack-Free Coverage
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Solution Overview
Problem
Existing semiconductor element mounting substrates face issues with insulating properties due to cracks in the insulating layer caused by thermal expansion coefficient differences, leading to potential short-circuiting when the layer is too thin or inadequate coverage when too thick.
Innovation Solution
A semiconductor element mounting substrate with a base composed of metal and an insulating layer having a maximum height, arithmetical mean height, and arithmetic mean roughness specified by ISO 25178 and JIS B 0601, respectively, that are equal to or less than the layer thickness, using materials like Al2O3 for improved insulation and copper for heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the insulating layer is made excessively thick to ensure complete coverage of the metal base, then the insulating property is improved, but cracks occur due to thermal expansion coefficient difference which degrades insulating properties
Solution Approach 1:
The patent applies parameter changes by precisely controlling the thickness of the insulating layer to be 10 micrometers or less, and controlling surface roughness parameters (maximum height Sz ≤ 4 micrometers, arithmetical mean height Sa ≤ 0.4 micrometers). This optimization of dimensional parameters reduces thermal stress while maintaining adequate insulation, preventing crack formation that would otherwise occur with thicker layers.
2Strength
If the insulating layer is made excessively thin to reduce thermal expansion stress, then crack generation is suppressed, but the insulating layer does not sufficiently cover the base causing short circuiting
Solution Approach 1:
The patent resolves this contradiction by establishing optimal parameter ranges: thickness of 10 micrometers or less combined with controlled surface roughness (Sz ≤ 4 micrometers, Sa ≤ 0.4 micrometers). These parameter specifications ensure the layer is thin enough to minimize thermal stress yet maintains sufficient coverage through controlled surface characteristics, preventing both cracking and short circuiting.
3Reliability
If the insulating layer thickness is increased to ensure coverage, then short circuiting is prevented, but the stress from thermal expansion difference increases causing crack formation
Solution Approach 1:
The patent applies parameter changes by setting the insulating layer thickness to 10 micrometers or less and controlling surface roughness parameters (maximum height Sz ≤ 4 micrometers, arithmetical mean height Sa ≤ 0.4 micrometers). This optimized parameter combination maintains adequate electrical insulation while minimizing thermal stress accumulation that would lead to cracking.
4Ease of manufacture
If the insulating layer is made thinner to reduce manufacturing complexity, then production cost decreases, but coverage becomes insufficient leading to short circuits
Solution Approach 1:
The patent establishes specific parameter thresholds (thickness ≤ 10 micrometers, Sz ≤ 4 micrometers, Sa ≤ 0.4 micrometers) that define the optimal manufacturing range. These parameters balance manufacturing simplicity with reliable insulation performance, providing clear manufacturing specifications that ensure adequate coverage without excessive thickness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances insulating properties by preventing cracks and voids, ensuring complete coverage and effective insulation between the base and electrode, while also providing efficient heat dissipation.
Implementation Method 1
cracks may occur due to the difference in thermal expansion coefficient with respect to the base
Implementation Method 2
a base composed of a metal
Data Source
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AI summary
A semiconductor element mounting substrate includes a base composed of a metal, an electrode to be connected to a semiconductor element, and an insulating layer disposed between the base and the electrode, in which a maximum height Sz (micrometers) of a base-side surface of the insulating layer specified by ISO 25178 is equal to or less than the thickness of the layer itself.