Movable-Tap Digital Equalizer for Low-Complexity ISI Reduction

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Solution Overview

Problem

High-speed digital communication systems face challenges in effectively combating inter-symbol interference (ISI) and noise, particularly as symbol rates increase, leading to increased power consumption and complexity in receiver designs.

Innovation Solution

The implementation of a digital equalizer apparatus and method utilizing movable taps, including a shift register, multipliers, multiplexers, and a summer, which allows for adaptive coefficient setting and selection of receive signal samples to produce a filtered output signal, effectively reducing ISI and noise amplification.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If increasing degrees of parallelism are employed to combat ISI at high symbol rates, then ISI reduction capability is improved, but power consumption increases to undesirable levels

Engineering Contradiction:
ImproveISI reduction capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements movable taps that can dynamically adjust their positions within the shift register based on channel conditions. This dynamic repositioning allows the equalizer to maintain effective ISI cancellation with fewer active multipliers, thereby reducing power consumption while preserving reliability at high symbol rates

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The equalizer changes the parameter of tap positions from fixed to variable/movable. By allowing taps to move to optimal positions, the system achieves better ISI reduction with reduced computational effort, lowering power consumption while maintaining or improving reliability

Inventive Principle:
Principle #35Parameter changes

2Reliability

If more filter taps are used to reduce ISI, then equalization performance is improved, but device complexity increases

Engineering Contradiction:
Improveequalization performanceVSAvoidhardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs movable taps that can reposition themselves to focus computational resources on the most significant ISI components. This dynamic adaptation allows effective equalization performance with a manageable number of active taps, avoiding the complexity of having all possible taps permanently implemented

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The shift register structure serves multiple functions: it stores received signal samples and provides them to movable taps at different positions. This multi-functionality reduces overall hardware complexity while maintaining equalization performance, as the same storage structure supports various tap configurations

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If fixed tap positions are used in the equalizer, then device complexity is reduced, but adaptability to different channel conditions deteriorates

Engineering Contradiction:
Improveequalizer structure simplicityVSAvoidchannel condition adaptability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent introduces movable taps that can dynamically adjust their positions within the shift register to adapt to different channel conditions. This dynamic capability provides versatility across various channel scenarios while maintaining relatively simple hardware architecture

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The equalizer changes the tap position parameter from fixed to variable, enabling adaptation to different channel conditions. This parameter change allows the same hardware structure to handle diverse scenarios, improving adaptability without significantly increasing complexity

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11171815B2Digital equalizer with overlappable filter taps
Publication Date: 2021.11.09 CREDO TECHNOLOGY GROUP LTD
  • US11171815B2 patent drawing
  • US11171815B2 patent drawing
  • US11171815B2 patent drawing

AI summary

In one illustrative embodiment, an equalizer includes: a shift register, an array of multipliers, an array of multiplexers, and a summer. The shift register provides receive signal samples at each tap. Each multiplier in the array multiplies one of said receive signal samples by a respective coefficient to produce a product, with at least one of said multipliers coupled to a fixed tap. Each multiplexer in the array supplies an associated one of said multipliers with a receive signal sample from a selectable tap. The summer sums the products to produce a filtered output signal. To reduce hardware requirements, coefficient multipliers may be multiplexed to a reduced set of taps, and the dynamic range of the coefficients may be increased by overlapping the sets for different multipliers. Methods of tap selection and coefficient adaptation are disclosed.