Multi-Project Chip Cost Reduction via Segmented Architecture
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Solution Overview
Problem
The existing multi-project wafer (MPW) semiconductor manufacturing process incurs exponentially increasing costs due to miniaturization, making it challenging for orderers to develop and mass-produce new chips, especially with the high costs of initial development, IP usage, and backend processes, limiting the ability to share hardware and software platforms effectively.
Innovation Solution
A multi-project chip (MP-chip) design that includes individual units driven by each orderer's security element and common units shared among orderers, reducing costs by optimizing the chip structure to minimize initial development and backend expenses, allowing multiple orderers to share IP and hardware resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multiple orderers share costs using known MPW arrangements, then initial development costs are reduced, but costs increase exponentially due to process miniaturization
Solution Approach 1:
The chip is divided into individual units ( privately designed by each orderer) and common units (shared by multiple orderers). This segmentation allows cost sharing for common units while maintaining private ownership of individual units, resolving the contradiction between cost sharing capability and cost amount.
Solution Approach 2:
Common units are designed to serve multiple orderers simultaneously, enabling one chip structure to fulfill multiple functions for different clients. This universality reduces the total number of chips that need to be manufactured, thereby reducing overall costs despite process miniaturization.
2Productivity
If chip size is reduced for miniaturization, then more chips can be produced per wafer, but initial development costs increase exponentially
Solution Approach 1:
Multiple individual units and common units are merged into a single multi-project chip structure. This combining allows the wafer to be utilized more efficiently by producing multiple chip types in one manufacturing run, increasing chips per wafer while the shared common units offset the increased development costs through cost pooling.
Solution Approach 2:
Common units are designed and manufactured in advance as shared resources before individual units are fully developed. This preliminary action reduces the overall development timeline and cost by preparing reusable components that can be quickly integrated with different individual units.
3Ease of manufacture
If more orderers share common units, then layout and backend costs are reduced, but chip design complexity increases
Solution Approach 1:
The chip architecture is segmented into standardized common units and customizable individual units. This segmentation simplifies the design process by providing modular building blocks that can be combined in different configurations, reducing overall design complexity while enabling cost sharing across multiple orderers.
Solution Approach 2:
The chip design allows for parameter changes in individual units while maintaining fixed common units. This flexibility enables orderers to customize their specific requirements without redesigning the entire chip, thereby reducing layout and backend costs despite increased overall chip variety.
Data Source
AI summary
This invention is about a multi-project chip or MP-chip that includes multiple individual units that can be selectively driven by multiple orders, and one or more common units that can be driven by two or more of the orders, respectively. In particular, the MP-chip may be installed inside the MP-chip or may be manufactured as a body separate the MP-chip or installed inside the MP-chip.