MPC Processor and Compiler for Low-Overhead Secure Computation
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Solution Overview
Problem
Existing MPC solutions face challenges such as high computational and communication overheads, and software-based solutions are inefficient, which existing technologies fail to effectively solve the performance bottlenecks and inefficiencies, and hardware-based solutions are ineffective, particularly in large-scale computations involving many parties, which can result in prohibitive computational and communication overheads, which can result in significant performance bottlenecks and inefficiencies.
Innovation Solution
A bespoke processor and compiler for XOR Secret share based MultiParty Computation (MPC) that includes a full development and execution framework, featuring a compiler, an MPC Instruction Set Architecture (ISA), an assembler, and a bespoke processor, which efficiently executes programs compiled with the ISA, addressing the inefficiencies and performance bottlenecks, and hardware optimization geared towards reducing communication and computational overheads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software-based circuit evaluation is used for MPC, then implementation flexibility is maintained, but significant computational overhead and performance bottlenecks occur
Solution Approach 1:
The patent replaces software-based circuit evaluation with a dedicated hardware processor designed specifically for MPC operations. The hardware architecture includes specialized units for evaluating encrypted logic gates and processing secret shares, eliminating the computational overhead inherent in software implementations while maintaining the flexibility of MPC applications.
2Productivity
If garbled circuits are used for hardware acceleration, then computational performance improves, but network overhead and hardware complexity increase significantly
Solution Approach 1:
The patent applies local quality by implementing XOR-based secret share operations specifically for overcoming network challenges in MPC. Rather than using complex garbled circuits throughout, the system uses simplified XOR operations for share manipulation and reserved communication channels for coordinate transformations, reducing overall hardware complexity while maintaining performance.
3Speed
If existing MPC hardware acceleration technologies are used, then computational speed improves, but network communication bottlenecks remain significant
Solution Approach 1:
The patent implements preliminary action by pre-establishing reserved communication channels for coordinate transformations and preparing secret share operations in advance. The hardware architecture includes dedicated units that can process encrypted logic gates and manage communication protocols efficiently, reducing the impact of network bottlenecks during execution.
Data Source
AI summary
A system for Multi-Party Computation (MPC) includes a general-purpose programming language, an MPC processor, an MPC Instruction Set Architecture (ISA), and a compiler. The general-purpose programming language is used for writing an MPC application. The MPC processor executes the MPC application. The MPC ISA corresponds to the MPC processor. The compiler generates an intermediate representation for the MPC application and generates machine code for the intermediate representation by mapping and assembling MPC ISA instructions.