MPE-FEC Erasure Cache Layout for Smaller DVB-H Receiver Memory
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Solution Overview
Problem
Existing DVB-H receiver designs face challenges in efficiently storing and accessing erasure location information due to large memory requirements and complex addressing schemes, which increase silicon area and power consumption, and complicate error correction processes.
Innovation Solution
The proposed solution involves grouping data bytes into data blocks and using a novel erasure cache RAM architecture with reduced memory size, employing (M+2)-bit or (M+1)-bit entries to indicate erasure status and potential boundary conditions, allowing for efficient column-wise and row-wise access, thereby minimizing memory size and logic complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If one bit is allocated for each data byte to flag erasure status, then complete erasure location information is stored, but memory size increases to 255 Kbits
Solution Approach 1:
The patent segments the erasure status information by grouping data bytes into data blocks of 2^M consecutive bytes. Instead of storing individual bit status for each byte, it stores consolidated block-level erasure status information, reducing memory requirements while maintaining error correction capability.
Solution Approach 2:
The patent introduces a new dimension of organization by using (M+2)-bit entries that encode both the number of erasures and their positions within blocks. This dimensional transformation allows compact representation of erasure patterns that would otherwise require linear scaling with data size.
2Quantity of substance
If indirect indexing is used to store erasure information, then memory size is reduced to 76 Kbits, but addressing complexity increases for row-wise access
Solution Approach 1:
The patent segments erasure information into fixed-size blocks of 2^M bytes, where M is a positive integer. This segmentation creates a regular, predictable memory structure that simplifies addressing compared to indirect indexing, while still achieving compact representation.
Solution Approach 2:
The patent changes the parameter representation from indirect addresses to direct block indices with embedded erasure counts. The (M+2)-bit entry format directly encodes erasure status and position information, eliminating the need for complex address translation logic.
3Productivity
If erasure information is stored in column-wise order, then storage is efficient, but row-wise access for RS decoding requires complex address calculation
Solution Approach 1:
The patent segments the MPE-FEC frame into regular blocks of 2^M consecutive bytes in column-wise order. This regular segmentation creates predictable access patterns that simplify the address calculation logic needed for row-wise access during RS decoding.
Solution Approach 2:
The patent introduces block-level indexing as an intermediary layer between column-wise storage and row-wise access requirements. The (M+2)-bit block entries serve as mediators that encode erasure information in a format accessible for both storage efficiency and decoding operations.
4Productivity
If MPE-FEC RAM size is increased to process multiple back-to-back channels, then channel processing capability is improved, but erasure cache memory size must increase proportionally
Solution Approach 1:
The patent segments erasure cache memory into independent block units that can be efficiently managed for multiple frames. This segmentation allows the same compact block structure to serve multiple back-to-back channels without proportional memory increases.
Solution Approach 2:
The patent creates a universal block-based erasure cache structure that serves multiple functions: storing erasure information for single or multiple frames, supporting both column-wise and row-wise access, and enabling processing of multiple back-to-back channels with fixed memory resources.
Data Source
AI summary
Location cache memory architectures that only require 32 Kbits or less per frame to store erasure information with simple address mapping to the main MPE-FEC RAM for easy column-wise and row-wise access. Alternative architectures are designed to greatly reduce the size and logic complexity of the MPE-FEC erasure cache memory. Two architectures reduce the erasure cache size down to 32 Kbits and 28 Kbits, correspondingly, without introducing additional erasure locations, while another architecture further reduces the required memory size down to 16K, 8K, 4K, or 2K bits with a slight increase in the total erasure locations. All architectures group the data in MPE-FEC frame memory into blocks of 2M consecutive bytes and use one or a few bits to store the erasure status in each block, thereby, greatly reducing the required cache memory size.