MPEG Processor Memory Architecture for Multi-Stream Parallel Processing

The patent divides the processing system into separate processing pipelines for different data streams, with each pipeline having its own decoder and memory resources. This segmentation allows parallel processing of multiple MPEG data streams while maintaining manageable memory requirements for each individual stream, thereby improving overall processing speed without proportionally increasing total memory requirements.

The patent implements a hierarchical memory architecture where stream-specific buffers are nested within a larger shared memory structure. Each data stream has its own dedicated buffer space, and these buffers are organized within a unified memory management framework. This nesting allows efficient access to stream-specific data while utilizing shared memory resources, resolving the contradiction between processing speed and memory requirements.

The patent designs memory controllers and buffer management systems that can handle multiple data streams universally through a single integrated structure. The same memory infrastructure and control logic serve all processing pipelines, allowing the system to process multiple streams efficiently without requiring separate dedicated memory subsystems for each stream, thereby reducing overall system complexity.

The patent combines multiple stream processing functions into unified processing units and shared memory resources. By merging common functionalities such as memory management, data buffering, and control logic into shared components that serve multiple streams, the system achieves high processing efficiency for multiple data streams while avoiding the complexity of completely separate processing chains for each stream.

The patent implements preliminary buffering and pre-processing stages where data from multiple streams is prepared and organized in advance in memory buffers before actual decoding begins. This preliminary action allows the system to maintain lower peak memory usage during active processing while still enabling parallel handling of multiple streams, thereby reducing both processing time and memory requirements simultaneously.

The patent transitions from sequential one-dimensional processing to parallel multi-dimensional processing by organizing multiple data streams into independent processing planes. Each stream is processed in its own temporal and spatial dimension within the processing architecture, allowing simultaneous execution without requiring proportional increases in memory resources, thus reducing both processing time and memory usage.