Clock Recovery for MPEG-2 Remultiplexing with Network Jitter
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Solution Overview
Problem
Cable networks face challenges in delivering seamless video due to network jitter introduced by IP/GbE technology, which violates the timing requirements of MPEG-2 standards, particularly in the transition from IP networks to HFC networks, requiring an efficient method to remove jitter and recover the source clock.
Innovation Solution
A clock recovery method and apparatus utilizing a dejittering filter followed by a phase lock loop to remove arrival time jitter and recover PCR clock rates, ensuring MPEG-2 compliance, even in the presence of constant bitrates, by selecting a master PCR PID and treating slave PCRs with additional treatment for time base offset correction, and applying these techniques to both MPTS and SPTS streams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If IP/GbE technology is used for video distribution, then network flexibility and service introduction capability are improved, but network jitter is introduced that violates MPEG timing requirements
Solution Approach 1:
The patent introduces an intermediary dejittering filter between the IP network and the HFC network to mediate the timing violations. This filter acts as a buffer that absorbs the jitter introduced by IP networking while maintaining MPEG-compliant timing for the downstream HFC delivery, thus resolving the contradiction between network flexibility and timing reliability
2Productivity
If multiple input streams are remultiplexed into a single output stream, then service consolidation is improved, but clock synchronization becomes more complex
Solution Approach 1:
The patent extracts the clock recovery function as a separate, dedicated module within the remultiplexer. By taking out the clock synchronization complexity into a standalone component, the main remultiplexing process can focus on service consolidation while the extracted clock module handles the timing complexity independently, thus resolving the contradiction between productivity and device complexity
3Reliability
If network jitter is removed through dejittering, then timing compliance is improved, but convergence rate of clock recovery becomes slower
Solution Approach 1:
The patent applies preliminary dejittering filtering to the incoming IP packets before they enter the clock recovery module. This preliminary action removes the bulk of the jitter upfront, allowing the subsequent phase-locked loop to converge faster to the correct clock frequency, thus resolving the contradiction between timing compliance and convergence speed
Data Source
AI summary
A method and apparatus for clock recovery for constant bit rate MPEG-2 compliant single program transport stream and multiple program transport stream delivered over UDP/IP is disclosed. Clock recovery utilizes a dejittering filter to remove arrival time jitter from received packets and a phase lock loop is used to recover a PCR clock rate up to a range allowed by the MPEG-2 System specification. An MPEG-2 compliant output stream is produced, even when the input PCR does not meet the timing requirement specified by the MPEG-2 System specification.