Massively Parallel Interconnect Fabric for 3D Stacked FPGA Dies
Solution Overview
Problem
Current FPGA technologies face limitations in terms of area, power consumption, form factor, performance, and cost-effectiveness, particularly in applications requiring low power consumption and high volume manufacturing, such as mobile devices, where they are not viable due to large die size and high power usage.
Innovation Solution
The solution involves a three-dimensional stacking of dies using a massively parallel interconnect fabric (MPIF) to connect logic blocks at the transistor/gate level, separating programming and context dies to reduce area and power consumption while maintaining flexibility, thereby creating a high-density, low-cost programmable platform ASIC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA uses programmable interconnects and storage elements on the same die as logic blocks, then reconfigurability is achieved, but die size increases and power consumption increases
Solution Approach 1:
The patent segments the FPGA architecture by separating the context die (containing logic blocks) from the programming die (containing interconnects and storage elements). This segmentation allows each die to be optimized independently, reducing the area overhead on the context die while maintaining full reconfigurability through the external interconnect fabric.
Solution Approach 2:
The patent transitions from a two-dimensional planar integration of all FPGA components to a three-dimensional stacked architecture using wafer-level packaging. The programming die is bonded to the context die, creating vertical interconnect paths that reduce the area footprint on each individual die while maintaining high-density connections.
2Adaptability or versatility
If FPGA uses programmable interconnects and storage elements on the same die as logic blocks, then reconfigurability is achieved, but power consumption increases
Solution Approach 1:
By segmenting the FPGA into separate context and programming dies, the patent enables independent power management. The context die can operate with lower power consumption since it lacks the power-intensive programmable interconnects and storage elements, which are relocated to the programming die.
Solution Approach 2:
The patent introduces an external interconnect fabric as an intermediary between the context die and programming die. This intermediary enables reconfigurability without requiring power-intensive on-die interconnects and storage elements on the context die, thereby reducing overall power consumption while maintaining adaptability.
3Ease of manufacture
If structured ASIC approach is used with customization at metallization layers, then NRE cost is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent moves the customization from the two-dimensional metallization layer to the three-dimensional wafer-level packaging domain. By bonding the programming die to the context die at the wafer level, the patent achieves structured ASIC cost benefits while enabling post-manufacturing reconfiguration through the external interconnect fabric.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces production costs, increases performance, and minimizes the time and cost associated with converting designs to high-volume production by decoupling core and context architecture, allowing for reconfigurability without affecting the core die, thus overcoming the limitations of traditional FPGAs.
Implementation Method 1
The examples of types of pad-pad connections include metal-metal, oxide bonding, capacitive bonding, conducting polymer to conducting polymer, and conducting semiconductor to conducting semiconductor.
Data Source
AI summary
An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.