MPI Parallel Synchronization Using CPU C-State Switching

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Solution Overview

Problem

Existing high-performance computing (HPC) systems face significant power consumption issues due to continuous polling mechanisms in Message Passing Interface (MPI) implementations, which keep CPU cores fully loaded during data message completion, despite minimal data movement or computational tasks.

Innovation Solution

Implement a software library that intercepts MPI function calls to enable C-state switching for processing elements (PEs), allowing PEs to transition to lower power states during message completion and reset to default states when ready, using instructions like UMONITOR/UMWAIT and MONITORX/MWAITX to manage CPU power states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If continuous polling mechanisms are used in MPI implementations to ensure message completion, then data integrity and communication reliability are improved, but CPU cores remain fully loaded consuming excessive power

Engineering Contradiction:

Improvemessage completion reliabilityVSAvoidCPU power consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the CPU state changeable between active polling and low-power wait states. The system transitions from a static fully-loaded CPU state to a dynamic state that adapts based on message completion status, allowing CPUs to enter C-state wait modes during polling intervals and resume activity only when needed, thus resolving the contradiction between continuous monitoring reliability and power consumption

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameter of CPU states from a fixed active state to variable states including C-state wait modes. By modifying the state parameter based on polling results and message completion status, the system reduces power consumption while maintaining reliable message completion detection, directly addressing the energy-reliability contradiction

Inventive Principle:

Principle #35Parameter changes

2Speed

If CPU cores remain fully loaded during message completion to ensure timely processing, then computational responsiveness is improved, but power consumption increases significantly

Engineering Contradiction:

Improvemessage processing speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSLoss of energy

Solution Approach 1:

The patent implements periodic action by using intermittent polling instead of continuous full-load processing. CPUs periodically check for message completion in low-power wait states rather than maintaining full computational capacity continuously, achieving timely processing when needed while minimizing energy loss during idle polling intervals

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The system applies self-service by allowing CPU cores to autonomously transition to low-power states during polling without external intervention. The polling mechanism itself serves the dual purpose of both monitoring and power management, with CPUs automatically resuming active states only when messages require processing, thus reducing energy loss while maintaining responsiveness

Inventive Principle:

Principle #25Self-service

3Productivity

If all CPU cores are kept active for parallel processing, then computational throughput is improved, but overall system power consumption increases

Engineering Contradiction:

Improvecomputational throughputVSAvoidsystem power consumption

Core Design Contradiction:

ProductivityVSUse of energy by stationary object

Solution Approach 1:

The patent applies segmentation by dividing CPU cores into different operational groups - some cores remain active for computational throughput while others enter low-power wait states during polling. This segmentation allows the system to maintain productivity through active cores while reducing overall system power consumption through inactive cores, resolving the throughput-energy contradiction

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS20250370757A1Power savings during parallel synchronization for distributed memory systems by using different processor states

Publication Date: 2025.12.04 DELL PROD LP

AI summary

Presented herein are embodiments that involve the CPU-intensive nature of parallel applications using message passing on multiple, distributed-memory server nodes. Power saving embodiments may be integrated into existing HPC (high-performance computing) applications using a message passing interface, which may be implemented using a software library. Tested embodiments showed savings of up to 17% of power consumption at the expense of a small performance penalty. In at least one case, an actual performance improvement was seen. It shall be noted that embodiments are not limited to parallel HPC workloads. One or more embodiments may be extended to every workload where either load imbalance or wait time for external data is involved, like shared storage systems, and distributed network operations for artificial intelligence/machine learning workloads.