Memory Protection Unit Segment Subsegment Registers
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Solution Overview
Problem
Conventional memory protection technologies, such as the MMU-based scheme, are not suitable for embedded multi-processor systems due to complex hardware requirements and limited local memory, leading to performance issues and increased overhead as the number of cores increases.
Innovation Solution
A memory protection method and apparatus that extracts segment and subsegment addresses from memory access attempts, comparing them with base addresses stored in segment and subsegment registers, and transmitting exception signals to the CPU when access is unauthorized, using a Memory Protection Unit (MPU) to determine and enforce access rights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MMU-based memory protection scheme is used, then memory access control is achieved, but hardware complexity increases
Solution Approach 1:
The patent extracts the memory protection function from the complex MMU hardware and implements it through simpler segment registers and a dedicated Memory Protection Unit (MPU) that monitors access rights, eliminating the need for full MMU hardware while maintaining memory protection capabilities
Solution Approach 2:
The patent segments the memory protection mechanism into distinct components: segment registers for storing base addresses, subsegment registers for offset tracking, and a separate MPU for enforcement, making the system more modular and less complex than a monolithic MMU
2Speed
If MMU with TLB is used, then address translation speed is improved, but hardware overhead increases
Solution Approach 1:
The patent removes the TLB component entirely and replaces it with a simplified register-based address translation mechanism where segment and subsegment registers directly store translation information, eliminating the need for cached page tables while maintaining fast access
Solution Approach 2:
Instead of implementing a full TLB cache mechanism, the patent uses partial registration of address translations in segment and subsegment registers, providing sufficient translation capability without the excessive hardware overhead of a complete TLB system
3Reliability
If page table is maintained in shared DRAM, then memory protection is achieved, but access performance decreases
Solution Approach 1:
The patent segments the address translation information into distributed segment and subsegment registers located in each processor's local memory, eliminating the need to maintain a centralized page table in shared DRAM and improving access performance by avoiding the performance penalty of shared memory access
Solution Approach 2:
The patent implements local address translation registers in each processor's local memory rather than using shared DRAM for page tables, allowing each processor to perform address translation locally without waiting for shared memory access, thereby improving access performance
4Reliability
If separate hardware for each core is implemented, then memory protection is achieved, but overhead increases with number of cores
Solution Approach 1:
The patent implements universal segment and subsegment register structures that can be shared across multiple cores with the same basic architecture, allowing each core to have memory protection capabilities without requiring separate dedicated hardware for each core, thereby reducing overhead as the number of cores increases
Data Source
AI summary
Memory mapping in small units using a segment and subsegments is described, and thus it is possible to control a memory access even using a small amount of hardware, and it is possible to reduce costs incurred by hardware. Additionally, it is possible to prevent a memory from being destroyed due to a task error in the multi-processor system.