Memory Protection Unit with Variable-Size Entries
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Solution Overview
Problem
Current memory protection units (MPUs) face challenges in efficiently controlling access to memory in real-time applications with constrained memory resources, as they often require large page table structures and limited memory protection entries, leading to performance issues and increased latency due to page faults and exceptions.
Innovation Solution
An MPU with a memory-based memory protection table that allows for variable-sized address regions and stores access permissions in the memory system, reducing the need for large page tables and minimizing exceptions by using a hybrid approach combining register-based and memory-based entries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a memory management unit (MMU) with page tables is used to control memory access, then access permissions can be defined for multiple address regions, but the system requires large page table structures and consumes significant memory resources
Solution Approach 1:
The patent extracts the memory protection table from the MMU hardware structure and stores it in the memory system itself. This separation allows the MMU to function with a smaller footprint while the protection table resides in memory, reducing the memory resources consumed by the MMU's internal page table structures.
Solution Approach 2:
The patent creates a copy of the memory protection table in the memory system that can be accessed by the MMU. This copied structure in memory allows the MMU to reference protection information without maintaining large page table structures in hardware, thereby reducing memory resource consumption while preserving access permission control capabilities.
2Adaptability or versatility
If an MMU with hierarchical page tables is used, then arbitrary address translations can be handled, but page faults and exceptions increase latency and reduce performance
Solution Approach 1:
The patent pre-loads and stores the memory protection table in the memory system before it is needed for address translation operations. By having the protection table readily available in memory rather than requiring hierarchical page table walks through the MMU, the system eliminates page faults and exceptions that would otherwise increase latency and reduce performance.
3Device complexity
If an MPU with limited protection entries is used, then hardware costs are reduced, but the number of simultaneously protected address regions is limited
Solution Approach 1:
The patent moves the protection table from the hardware dimension (MPU registers) to the memory dimension (memory system storage). This dimensional shift allows the system to support a large number of protected address regions by storing protection entries in memory rather than being constrained by the limited number of hardware registers available in the MPU, while keeping hardware costs low.
4Adaptability or versatility
If memory protection entries are stored in memory system, then more entries can be supported without increasing hardware costs, but access time to protection information may increase
Solution Approach 1:
The patent optimizes the memory system by placing the memory protection table in a readily accessible location within the memory hierarchy. This local optimization ensures that while protection information is stored in memory rather than hardware registers, the access time is minimized by positioning the protection table close to the MMU or in high-speed memory, thereby supporting more protection entries without significantly increasing access time.
Data Source
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AI summary
An apparatus comprises processing circuitry to issue memory access requests specifying a target address identifying a location to be accessed in a memory system; and a memory protection unit (MRU) comprising permission checking circuitry to check whether a memory access request issued by the processing circuitry satisfies access permissions specified in a memory protection table stored in the memory system. The memory protection table comprises memory protection entries each specifying access permissions for a corresponding address region of variable size within an address space, where the variable size can be a number of bytes other than a power of 2.