MPW Mask IP Protection via Chiplet Pattern Modification
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Solution Overview
Problem
The miniaturization of portable consumer products like MP3 players and mobile phones requires smaller integrated circuits with high memory density and functionality, leading to higher production costs, and existing Multi-Project-Wafer (MPW) technologies expose intellectual property (IP) resources to competitors, necessitating a solution for reducing fabrication costs while ensuring IP protection.
Innovation Solution
A method involving the use of Multi-Project-Wafer (MPW) masks with IP protection to form devices, where non-relevant chiplets of an IP owner are modified to obscure their IP information, ensuring that only the relevant IP owner can access the IP, thereby preventing disclosure to non-relevant parties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If MPW technology is used to integrate multiple different designs on wafers, then production cost is reduced, but IP resources are exposed to third parties including competitors
Solution Approach 1:
The patent segments the wafer into multiple distinct regions, each containing chiplets from different IP owners. This spatial segmentation allows simultaneous fabrication of multiple designs on a single wafer while maintaining logical separation of IP resources. Each IP owner's designs are confined to specific regions, enabling cost-effective MPW fabrication while preventing unauthorized access to other parties' IP through physical and logical isolation boundaries.
2Productivity
If multiple IP owners' designs are integrated on the same wafer, then fabrication efficiency is improved, but IP security is compromised
Solution Approach 1:
The patent applies local quality by implementing distinct isolation mechanisms for different regions on the wafer. Each IP owner's region receives tailored isolation treatments (such as deep trenches, dielectric layers, or metallurgical barriers) specific to their IP protection requirements. This localized approach maintains high fabrication efficiency through shared processing steps while ensuring each region has appropriate IP security measures customized to its needs.
Solution Approach 2:
The patent introduces intermediary structures between different IP owners' designs, such as isolation trenches, dielectric barriers, or neutral buffer regions. These intermediaries act as mediators that physically separate competing IP resources while allowing the entire wafer to be processed together. The intermediary structures prevent direct interaction between different IP blocks, maintaining IP security without sacrificing the productivity benefits of multi-project wafer fabrication.
3Adaptability or versatility
If non-relevant chiplets are provided to relevant IP owners, then device functionality is improved, but IP information disclosure risk increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring isolation structures and protection mechanisms during the mask design and fabrication preparation stages. Before the actual wafer fabrication begins, each IP owner's chiplets are pre-isolated using techniques such as forming deep isolation trenches, applying protective dielectric layers, or configuring metallurgical barriers. This preliminary protection ensures that when non-relevant chiplets are present on the wafer for functionality testing, the IP information remains securely isolated and cannot be disclosed to non-authorized parties.
Data Source
AI summary
Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.