Multi-Project Wafer with Selective Die Inoperability
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Solution Overview
Problem
Conventional Multi Project Wafer (MPW) services cannot meet customers' needs for performing customer-premises performance tests and System in Package (SIP) development on bare chips, as they do not allow for the differentiation of operable and inoperable dies on the same wafer, which is essential for protecting intellectual property and facilitating testing.
Innovation Solution
A method of fabricating a semiconductor wafer with a combination of operable and inoperable dies, where the inoperable dies are rendered so by cutting or removing back-end-of-line layers, allowing the wafer to be provided to customers for testing while maintaining the operability of the other dies, and incorporating an unpatterned annular ring to enhance uniform grinding and reduce wafer breakage during processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all dies on the wafer are kept operable to maximize utilization of the mask set, then manufacturing efficiency is improved, but intellectual property protection deteriorates as other customers' designs remain accessible
Solution Approach 1:
The patent applies local quality by treating different regions of the wafer differently - some dies are rendered inoperable while others remain operable. This is achieved by selectively modifying specific dies through dicing, thinning, or chemical treatment to prevent access to certain customers' intellectual property while preserving access to others' designs, thus resolving the contradiction between maximizing mask set utilization and protecting intellectual property.
2Ease of operation
If the wafer is diced into individual dies for delivery, then customer-specific delivery is improved, but the ability to perform wafer-level testing deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the wafer into different zones - some areas are diced into individual dies for customer-specific delivery, while other areas remain undiced to maintain wafer-level testing capability. This selective segmentation allows both customer-specific delivery and wafer-level testing to coexist, resolving the contradiction between ease of operation and reliability.
3Productivity
If conventional dicing is performed on the entire wafer, then manufacturing efficiency is improved, but wafer breakage during subsequent processing increases
Solution Approach 1:
The patent applies partial action by performing dicing only on specific portions of the wafer rather than the entire wafer. By selectively dicing only the areas needed for customer delivery while leaving other areas intact, the wafer maintains sufficient structural integrity to prevent breakage during subsequent processing steps like thinning and chemical treatment, thus resolving the contradiction between manufacturing efficiency and wafer structural integrity.
Data Source
AI summary
A semiconductor wafer is fabricated. The wafer has a plurality of dies. The plurality of dies include at least operable dies of a first type and operable dies of a second type different from the first type. The dies of the second type are rendered inoperable, while keeping the dies of the first type operable. The wafer is provided with the operable dies of the first type and the inoperable dies of the second type on it, for testing of the dies of the first type.