MRAM Access Device Body-Biasing Leakage Control
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Solution Overview
Problem
In computing devices, particularly those using MRAM cells, high current signals for memory operations lead to increased opportunities for undesirable current leakage, which existing technologies have not effectively controlled.
Innovation Solution
The implementation of a circuit and method that includes body-biasing transistor access devices and controlling the gate-to-source voltage to reduce leakage current, using a current source and voltage source configuration that limits leakage to negligible amounts, specifically by applying a positive voltage to the source region relative to the gate region of unselected transistor access devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high current signals are used for memory operations in MRAM cells, then memory operation effectiveness is improved, but current leakage through unselected access devices increases
Solution Approach 1:
The patent applies body-biasing voltage to the access devices to dynamically adjust their electrical characteristics. By changing the body voltage parameter, the threshold voltage of unselected access devices is increased, thereby reducing leakage current while allowing selected devices to maintain high current conduction for effective memory operations
Solution Approach 2:
The patent segments the control of different access devices by individually applying body-biasing voltages to unselected devices while allowing selected devices to operate with normal biasing. This segmentation enables differential control where leakage reduction is applied only where needed, preserving high current conduction in selected devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively controls leakage current through unselected transistor access devices, reducing it to very small values while maintaining increased current conduction through selected MRAM cells, thereby minimizing heat dissipation and operational inefficiencies.
Implementation Method 1
each access device of the array may be coupled to a body-biasing voltage to increase a threshold voltage of the access device
Implementation Method 2
a current source at a second side of the array configured to generate the increased current conducted through each element of the array and to control leakage current conducted through each element of the array, wherein a gate voltage applied to a gate region of the access device included in each element of the array and the current source may cooperate to bring about a gate-to-source voltage
Data Source
AI summary
Briefly, the disclosure relates to circuits utilized to perform writing operations to a memory array, in which elements of the array comprise resistive memory cells coupled in series with an access device. In one embodiment, a circuit may comprise a supply voltage coupled to a first side of the array and a current source coupled to a second side of the array. The access devices of the elements of the array may be body-biased, which may operate to reduce the turn-on voltage (VTH) of the access devices. Particular voltages may be applied to gate regions of the access devices to control leakage current to the resistive memory cells of the array.